
Last Modified: October 2, 2017
Many of the papers below have been made available in PDF format for easy access. Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.
Publications

A. B. Kahng,
"Fast Hypergraph Partition",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1989,
pp. 762766.

A. B. Kahng,
"Traveling Salesman Heuristics and Embedding Dimension in the Hopfield Model",
(.ps),
(.pdf),
Proc. IEEE/INNS Intl. Joint Conf. on Neural Networks,
June 1989,
pp. I513  I520.

A. B. Kahng and G. Robins,
"A New Class of Steiner Tree Heuristics with Good Performance: the Iterated 1Steiner Approach",
(.ps),
(.pdf),
Proc. IEEE International Conf. on ComputerAided Design,
November 1990,
pp. 428431
(Distinguished Paper Award; 18 awards out of 442 submissions).

A. B. Kahng, J. Cong and G. Robins,
"HighPerformance Clock Routing Based on Recursive Geometric Matching",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1991,
pp. 322327.

A. B. Kahng,
"A Steiner Tree Construction for VLSI Routing",
(.ps),
(.pdf),
Proc. IEEE/INNS Intl. Joint Conf. on Neural Networks,
July 1991,
pp. I133  I139.

A. B. Kahng and G. Robins,
"Optimal Algorithms for Determining Regularity in Pointsets",
Proc. Third Canadian Conf. on Computational Geometry,
August 1991,
pp. 167170.

J. Cong, L. Hagen and A. B. Kahng,
"Random Walks for Circuit Clustering",
(.ps),
(.pdf),
Proc. 4th IEEE Intl. ASIC Conf.,
September 1991,
pp. 14.2.1  14.2.4.

J. Cong, A. B. Kahng and G. Robins,
"On Clock Routing For General Cell Layouts",
(.ps),
(.pdf),
Proc. 4th IEEE Intl. ASIC Conf.,
September 1991,
pp. 14.5.1  14.5.4.

J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong,
"PerformanceDriven Global Routing for Cell Based IC's",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on Computer Design,
October 1991,
pp. 170173.

A. B. Kahng,
"An Effective Analog Approach to Steiner Routing",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on Computer Design,
October 1991,
pp. 166169.

L. Hagen and A. B. Kahng,
"Fast Spectral Methods for Ratio Cut Partitioning and Clustering",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on ComputerAided Design,
November 1991,
pp. 1013.

A. B. Kahng,
"Exploiting Fractalness in Error Surfaces: New Methods for Neural Network Learning",
(.ps),
(.pdf),
Proc. IEEE Intl. Symp. on Circuits and Systems,
May 1992,
pp. 4144.

A. B. Kahng, G. Robins and E. Walkup,
"New Results and Algorithms for MCM Substrate Testing",
(.ps),
(.pdf),
Proc. IEEE Intl. Symp. on Circuits and Systems,
May 1992,
pp. 11131116.

J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong,
"Provably Good Algorithms for PerformanceDriven Global Routing",
(.ps),
(.pdf),
Proc. IEEE Intl. Symp. on Circuits and Systems,
May 1992,
pp. 22402243.

K. C. Chen, J. Cong, A. Kahng and P. Trajmar,
"DAGMAP: Graph Based FPGA Technology Mapping for Delay Optimization",
Proc. IEEE Workshop on FieldProgrammable Gate Arrays,
March 1992,
pp. 7781.

A. B. Kahng,
"Random Structure of Error Surfaces: Toward New Stochastic Learning Methods", invited paper,
(.ps),
(.pdf),
Proc. SPIE (Joint Conf. on Artificial Neural Networks: Science and Applications),
1710 (pt. 1, vol. 2) April 1992,
pp. 768779.

J. Cong, L. Hagen and A. B. Kahng,
"Net Partitions Yield Better Module Partitions",
(.ps),
(.pdf),
Proc. 29th ACM/IEEE Design Automation Conf.,
June 1992,
pp. 4752
(nominated for Best Paper Award; 18 nominees out of 440 submissions).

L. Hagen, A. B. Kahng, F. Kurdahi and C. Ramachandran,
"On the Intrinsic Rent Parameter and New SpectraBased Methods for Wireability Estimation",
(.ps),
(.pdf),
Proc. European Design Automation Conf.,
October 1992,
pp. 202208
(nominated for Best Paper Award; 6 nominees out of 335 submissions).

K. C. Chen, Y. Ding, J. Cong, A. Kahng and P. Trajmar,
"An Improved Graph Based FPGA Technology Mapping Algorithm for Delay Optimization",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on Computer Design,
October 1992,
pp. 154158.

K. Boese and A. B. Kahng,
"ZeroSkew Clock Routing Trees With Minimum Wirelength",
(.ps),
(.pdf),
Proc. IEEE 5th Intl. ASIC Conf.,
September 1992,
pp. 1.1.1  1.1.5.

L. Hagen and A. B. Kahng,
"Improving the Quadratic Objective Function in Module Placement",
(.ps),
(.pdf),
Proc. IEEE 5th Intl. ASIC Conf.,
September 1992,
pp. 1.7.1  1.7.4.

L. Hagen and A. B. Kahng,
"A New Approach to Effective Circuit Clustering",
(.ps),
(.pdf)
Proc. IEEE Intl. Conf. on ComputerAided Design,
November 1992,
pp. 422427.

K. D. Boese, J. Cong, A. B. Kahng, K. S. Leung and D. Zhou,
"On HighSpeed VLSI Interconnects: Analysis and Design",
(.ps),
(.pdf)
Proc. AsiaPacific Conf. on Circuits and Systems,
December 1992,
pp. 3540.

K. D. Boese and A. B. Kahng,
"Simulated Annealing of Neural Networks: the 'Cooling' Strategy Revisited",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on Circuits and Systems,
May 1993,
pp. 25722575.

C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh,
"Minimum Density Interconnection Trees",
(.ps),
(.pdf)
Proc. IEEE Intl. Conf. on Circuits and Systems,
May 1993,
pp. 18651868.

C. J. Alpert, T. C. Hu, J. H. Huang and A. B. Kahng,
"A Direct Combination of the Prim and Dijkstra Constructions for Improved PerformanceDriven Global Routing",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on Circuits and Systems,
May 1993,
pp. 18691872.

C. J. Alpert and A. B. Kahng,
"Geometric Embeddings for Faster (and Better) MultiWay Netlist Partitioning",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1993,
pp. 743748.

K. D. Boese, A. B. Kahng and G. Robins,
"HighPerformance Routing Trees With Identified Critical Sinks",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1993,
pp. 182187.

K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins,
"Toward Optimal Routing Trees",
(.ps),
(.pdf),
Proc. ACM SIGDA Physical Design Workshop,
April 1993,
pp. 4451.

K. D. Boese, A. B. Kahng and C.W. A. Tsao,
"BestSoFar vs. WhereYouAre: New Perspectives on Simulated Annealing for CAD",
(.ps),
(.pdf),
Proc. European Design Automation Conf.,
September 1993,
pp. 7883.

K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins,
"Fidelity and NearOptimality of ElmoreBased Routing Constructions",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on Computer Design,
October 1993,
pp. 8184.

C. J. Alpert and A. B. Kahng,
"MultiWay Partitioning Via Spacefilling Curves and Dynamic Programming",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1994,
pp. 652657.
(Best Paper Award out of 439 submissions.)

A. B. Kahng and S. Muddu,
"Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1994,
pp. 563569.

K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins,
"Rectilinear Steiner Trees with Minimum Elmore Delay",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1994,
pp. 381386.

A. B. Kahng and S. Muddu,
"Optimal Equivalent Circuits for Interconnect Delay Calculations Using Moments",
(.ps),
(.pdf),
Proc. European Design Automation Conference,
September 1994,
pp. 164169.

A. B. Kahng and C.W. A. Tsao,
"PlanarDME: Improved Planar ZeroSkew Clock Routing with Minimum Pathlength Delay",
(.ps),
(.pdf),
Proc. European Design Automation Conference,
September 1994,
pp. 440445.
(Nominated for Best Paper Award; 7 nominees out of 260 submissions.)

A. B. Kahng and C.W. A. Tsao,
"LowCost Planar Clock Trees With Exact Zero Elmore Delay Skew",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on ComputerAided Design,
November 1994,
pp. 213218.

C. J. Alpert and A. B. Kahng,
"A General Framework for Vertex Orderings, With Applications to Netlist Clustering",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on ComputerAided Design,
November 1994,
pp. 6367.

A. B. Kahng and S. Muddu,
"TwoPole Analysis of Interconnection Trees",
(.ps),
(.pdf),
Proc. IEEE MultiChip Module Conference,
February 1995,
pp. 105110.

J. H. Huang and A. B. Kahng,
"MultiWay System Partitioning into a Single Type or Multiple Types of FPGAs",
(.ps),
(.pdf),
Proc. ACM Intl. Symp. on FieldProgrammable Gate Arrays,
February 1995,
pp.
140145.

J. H. Huang and A. B. Kahng,
"When Clusters Meet Partitions: New DensityBased Methods for Circuit Decomposition",
(.ps),
(.pdf),
Proc. European Design and Test Conference,
March 1995,
pp. 6064.

K. D. Boese, D. E. Franklin and A. B. Kahng,
"Training Minimal Artificial Neural Network Architectures for Subsoil Object Detection",
(.ps),
(.pdf),
Proc. SPIE Aerosense95: Detection Technologies for Mines and Minelike Targets,
April 1995,
pp. 900911.

D. E. Franklin, A. B. Kahng and M. A. Lewis,
"Distributed Sensing and Probing With Multiple Search Agents: Toward SystemLevel Landmine Detection Solutions",
(.ps),
(.pdf),
Proc. SPIE Aerosense95: Detection Technologies for Mines and Minelike Targets,
April 1995,
pp. 698709.

L. Hagen, J. H. Huang and A. B. Kahng,
"Quantified Suboptimality of VLSI Layout Heuristics",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1995,
pp. 216221.

J. H. Huang, A. B. Kahng and C.W. A Tsao,
"On the BoundedSkew Clock and Steiner Routing Problems",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1995,
pp. 508513.

Y. Cao, T.W. Chen, M. Harris, A. B. Kahng, M. A. Lewis and A. D. Stechert,
"A Remote Robotics Laboratory on the Internet",
(.ps),
(.pdf),
Proc. INET95,
June 1995,
pp. 6572.

A. B. Kahng and B. R. Moon,
"Toward More Powerful Recombinations",
(.ps),
(.pdf),
Proc. Intl. Conf. on Genetic Algorithms,
July 1995,
pp. 96103.

Y. Cao, A. S. Fukunaga, A. B. Kahng and F. Meng,
"Cooperative Mobile Robotics: Antecedents and Directions",
(.ps),
(.pdf),
Proc. IEEE/RSJ Intl. Symp. on Intelligent Robotics and Systems,
August 1995,
pp. 226234.

L. Hagen, J. H. Huang and A. B. Kahng,
"On Implementation Choices for Iterative Improvement Partitioning Algorithms",
(.ps),
(.pdf),
Proc. European Design Automation Conf.,
September 1995,
pp. 144149.

J. Cong, A. B. Kahng, C. K. Koh and C.W. A. Tsao,
"BoundedSkew Clock and Steiner Routing Under Elmore Delay",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on ComputerAided Design,
November 1995,
pp. 6671.

A. S. Fukunaga and A. B. Kahng,
"Improving the Performance of Evolutionary Optimization by Dynamically Scaling the Evaluation Function",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on Evolutionary Computation,
November 1995,
pp. I182  I187.

I. Hong, A. B. Kahng and B. R. Moon,
"Exploiting Synergies of Multiple Crossovers: Initial Studies",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on Evolutionary Computation,
November 1995,
pp. I245  I250.

A. B. Kahng and S. Muddu,
"Efficient Gate Delay Modeling for Large Interconnect Loads",
(.ps),
(.pdf),
Proc. IEEE MultiChip Module Conference,
February 1996,
pp. 202207.

C. J. Alpert, L. Hagen and A. B. Kahng,
"A Hybrid Multilevel/Genetic Approach for Circuit Partitioning",
(.ps),
(.pdf),
Proc. ACM SIGDA Physical Design Workshop,
April 1996,
pp. 100105.

A. B. Kahng and S. Muddu,
"An Analytical Delay Model for RLC Interconnects",
(.ps),
(.pdf),
Proc. IEEE Intl. Symp. on Circuits and Systems,
May 1996,
pp. IV/237240.

A. B. Kahng and S. Muddu,
"New Analyses of Distributed RC Interconnections",
(.ps),
(.pdf),
Proc. IEEE Intl. Symp. on Circuits and Systems,
May 1996,
pp. IV/241244.

A. S. Fukunaga, J. H. Huang and A. B. Kahng,
"LargeStep Markov Chain Variants for VLSI Netlist Partitioning",
(.ps),
(.pdf),
Proc. IEEE Intl. Symp. on Circuits and Systems,
May 1996,
pp. IV/496499.

C. J. Alpert and A. B. Kahng,
"Simple EigenvectorBased Circuit Clustering Can Be Effective",
(.ps),
(.pdf),
Proc. IEEE Intl. Symp. on Circuits and Systems,
May 1996,
pp. IV/683686.

A. B. Kahng and S. Muddu,
"Analysis of RC Interconnections Under Ramp Input",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conference,
June 1996,
pp. 533538.

A. B. Kahng, K. Masuko and S. Muddu,
"Analytical Delay Models for VLSI Interconnections Under Ramp Input",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Conference on ComputerAided Design,
November 1996,
pp. 3036.

A. B. Kahng and S. Muddu,
"Delay Analysis of Coupled Transmission Lines",
(.ps),
(.pdf),
Proc. AsiaPacific Conference on Circuits and Systems,
November 1996,
pp. 8184.

A. B. Kahng and S. Muddu,
"Gate Load Delay Computation Using Analytical Models",
(.ps),
(.pdf),
Proc. AsiaPacific Conference on Circuits and Systems ,
November 1996,
pp. 433436.

C. J. Alpert, L. W. Hagen and A. B. Kahng,
"A Hybrid Multilevel/Genetic Approach for Circuit Partitioning",
(.ps),
(.pdf),
Proc. AsiaPacific Conference on Circuits and Systems,
November 1996,
pp. 298301.

A. B. Kahng, K. Masuko and S. Muddu,
"Delay Models for MCM Interconnects When Response is NonMonotone",
(.ps),
(.pdf),
Proc. IEEE MultiChip Module Conference,
March 1997,
pp. 102107.

C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet and K. Yan,
"Faster Minimization of Linear Wirelength for Global Placement",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 1997,
pp. 411.

D. J. Huang and A. B. Kahng,
"PartitioningBased StandardCell Global Placement with an Exact Objective",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 1997,
pp. 1825.

J. Cong, A. B. Kahng and K.S. Leung,
"Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 1997,
pp. 8895.

C. J. Alpert, D. J. Huang and A. B. Kahng,
"Multilevel Circuit Partitioning",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Design Automation Conference,
June 1997,
pp. 530533.

J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.C. Yen,
"Analysis and Justification of a Simple, Practical 2 1/2D Capacitance Extraction Methodology",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Design Automation Conference,
June 1997,
pp. 627632.

A. B. Kahng and C.W. A. Tsao,
"More Practical BoundedSkew Clock Routing",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Design Automation Conference,
June 1997,
pp. 594599.

C. J. Alpert, T. Chan, D. J.H. Huang, I. Markov and K. Yan,
"Quadratic Placement Revisited",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Design Automation Conference,
June 1997,
pp. 752757.

W. Huang and A. B. Kahng,
"A Layout Advisor for TimingCritical Bus Routing",
(.ps),
(.pdf),
(slides),
Proc. IEEE ASIC Conference,
September 1997,
pp. 210214.

A. B. Kahng, S. Muddu, E. Sarto and R. Sharma,
"Interconnect Tuning Strategies for HighPerformance ICs",
(.ps),
(.pdf),
(slides),
Proc. Design, Automation and Test in Europe,
February 1998.

A. E. Caldwell, A. B. Kahng, S. Mantik and I. L. Markov,
"Implications of AreaArray I/O for RowBased Placement Methodology",
(.ps),
(.pdf),
(slides),
Proc. IEEE Symp. on IC/Package Design Integration,
February 1998,
pp. 9398.

A. B. Kahng, G. Robins, A. Singh, H. Wang and A. Zelikovsky,
"Filling and Slotting: Analysis and Algorithms",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 1998,
pp. 95102.

A. B. Kahng and S. Muddu,
"New Efficient Algorithms for Computing Effective Capacitance",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 1998,
pp. 147151.

A. B. Kahng,
"Futures for Partitioning in Physical Design",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 1998,
pp. 190193.

A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky,
"On Wirelength Estimations for RowBased Placement",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 1998,
pp. 411.

A. B. Kahng, J. Lach, W. H. MangioneSmith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe,
"Watermarking Techniques for Intellectual Property Protection"
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conference,
June 1998,
pp. 776781.

A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe,
"Robust IP Watermarking Methodologies for Physical Design",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Design Automation Conference,
June 1998,
pp. 782787.

A. E. Caldwell, A. B. Kahng and I. L. Markov,
"Relaxed Partitioning Balance Constraints in TopDown Placement",
(.ps),
(.pdf),
(slides),
Proc. IEEE ASIC Conference,
September 1998,
pp. 229232.

A. B. Kahng, H. Wang and A. Zelikovsky,
"Automated Layout and Phase Assignment Techniques for Dark Field Alternating PSM",
(.ps),
(.pdf),
(.ppt),
Proc. 18th BACUS Symposium on Photomask Technology and Management,
September 1998,
pp. 222231.

A. B. Kahng,
"IC Layout and Manufacturability: Critical Links and Design Flow Implications",
(.ps),
(.pdf),
(slides),
Proc. IEEE Intl. Conf. on VLSI Design,
Jan. 1999,
pp. 100105.

A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky,
"New and Exact Filling Algorithms for Layout Density Control",
(.ps),
(.pdf),
(slides),
Proc. IEEE Intl. Conf. on VLSI Design,
Jan. 1999,
pp. 106110.

A. B. Kahng, S. Muddu, E. Sarto,
"Interconnect Optimization Strategies for HighPerformance VLSI Design",
(.ps),
(.pdf),
Proc. IEEE Intl. Conf. on VLSI Design,
Jan. 1999,
pp. 464469.

A. B. Kahng and S. Muddu,
"Improved Effective Capacitance Computations for Use in Logic and Layout Optimization",
(.ps),
(.pdf),
(slides),
Proc. IEEE Intl. Conf. on VLSI Design,
Jan. 1999,
pp. 578582.

A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky,
"New Multilevel and Hierarchical Algorithms for Layout Density Control",
(.ps),
(.pdf),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 1999,
pp. 221224.

R. Baldick, A. B. Kahng, A. Kennings and I. L. Markov,
"Function Smoothing with Applications to VLSI Layout",
(.ps),
(.pdf),
(slides),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 1999,
pp. 225228.
(Nominated for Best Paper award).

A. B. Kahng , P. Tucker and A. Zelikovsky,
"Optimization of Linear Placements for Wirelength Minimization with Free Sites",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 1999,
pp. 241244.
(Nominated for Best Paper award).

A. E. Caldwell, A. B. Kahng and I. L. Markov,
"Design and Implementation of the FiducciaMattheyses Heuristic for VLSI Netlist Partitioning",
(.ps),
(.pdf),
(slides),
Proc. Workshop on Algorithm Engineering and Experimentation (ALENEX),
Jan. 1999,
pp. 177193

P. Berman, A. B. Kahng, D. Vidhani, H. Wang and A. Zelikovsky,
"Optimal Phase Conflict Removal for Layout of Dark Field Alternating Phase Shifting Masks",
(.ps),
(.pdf),
(slides),
Proc. ACM Intl. Symp. on Physical Design,
April 1999,
pp. 121126.

A. E. Caldwell, A. B. Kahng and I. L. Markov,
"Optimal Partitioners and EndCase Placers for StandardCell Layout",
(.ps),
(.pdf),
(slides),
Proc. ACM Intl. Symp. on Physical Design,
April 1999,
pp. 9096.

C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov,
"Partitioning With Terminals: A 'New' Problem and New Benchmarks",
(.ps),
(.pdf),
(slides),
Proc. ACM Intl. Symp. on Physical Design,
April 1999,
pp. 151157.

A. B. Kahng and Y. C. Pati,
"Subwavelength Optical Lithography: Challenges and Impact on Physical Design",
(.ps),
(.pdf),
(slides),
Proc. ACM Intl. Symp. on Physical Design,
April 1999,
pp. 112119.

A. E. Caldwell, A. B. Kahng, A. A. Kennings and I. L. Markov,
"Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 1999,
pp. 349354.

A. E. Caldwell, A. B. Kahng and I. L. Markov,
"Hypergraph Partitioning with Fixed Vertices",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 1999,
pp. 355359.

A. E. Caldwell, H.J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak and G. Qu,
"Effective Iterative Techniques for Fingerprinting Design IP",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1999,
pp. 843848.

A. B. Kahng and Y. C. Pati,
"Subwavelength Lithography and its Potential Impact on Design and EDA",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 1999,
pp. 799804.

P.Berman, A. B. Kahng, D. Vidhani and A. Zelikovsky,
"The TJoin Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout",
(.ps),
(.pdf),
Proc. Workshop on Algorithms and Data Structures (WADS), LNCS(vol. 1663),
August 1999,
pp. 2536.

A. B. Kahng, S. Muddu and D. Vidhani,
"Noise and Delay Uncertainty Studies for Coupled RC Interconnects",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE International ASIC/SOC Conference,
September 1999,
pp. 38.

Y. Chen, A. B. Kahng, G. Qu and A. Zelikovsky,
"The AssociativeSkew Clock Routing Problem",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 1999,
pp. 168172.

A. B. Kahng, D. Kirovski, S. Mantik, M. Potkonjak and J. L. Wong,
"Copy Detection for Intellectual Property Protection of VLSI Design",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 1999,
pp. 600604.

A. E. Caldwell, A. B. Kahng and I. L. Markov,
"Improved Algorithms for Hypergraph Bipartitioning",
(.ps),
(.pdf),
(slides),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2000,
pp. 661666.

Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky,
"MonteCarlo Algorithms for Layout Density Control",
(.ps),
(.pdf),
(slides),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2000,
pp. 523528.

A. B. Kahng, S. Mantik and D. Stroobandt,
"Requirements for Models of Achievable Routing",
(.ps),
(.pdf),
(.ppt),
Proc. ACM Intl. Symp. on Physical Design,
April 2000,
pp. 411.

A. B. Kahng,
"Classical Floorplanning Harmful?",
(.ps),
(.pdf),
(.ppt),
Proc. ACM Intl. Symp. on Physical Design,
April 2000,
pp. 207213.

A. B. Kahng and D. Stroobandt,
"Wiring Layer Assignments with Consistent Stage Delays",
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
April 2000,
pp. 115122.

A. B. Kahng, S. Muddu and E. Sarto,
"On Switch Factor Based Analysis of Coupled RC Interconnects",
(.ps),
(.pdf),
Proc. ACM/IEEE Design Automation Conf.,
June 2000,
pp. 7984.

A. E. Caldwell, A. B. Kahng and I. L. Markov,
"Can Recursive Bisection Alone Produce Routable Placements?",
(.ps),
(.pdf),
((.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2000,
pp. 477482.

Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky,
"Practical Iterated Fill Synthesis for CMP Uniformity",
(.ps),
(.pdf),
((.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2000,
pp. 671674.

A. E. Caldwell, Y Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. R. Oliver, D. Stroobandt and D. Sylvester,
"GTX: The MARCO GSRC Technology Extrapolation System",
(.ps),
(.pdf),
((.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2000,
pp. 693698.

S. Fenstermaker, D. George, A. B. Kahng, S. Mantik and B. Thielges,
"METRICS: A System Architecture for Design Process Optimization",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2000,
pp. 705710.

A. B. Kahng and S. Mantik,
"On Mismatches Between Incremental Optimizers and Instance Perturbations in Physical Design Tools",
(.ps),
(.pdf),
((.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 2000,
pp. 1721.

Y. Cao, C. M. Hu, X. J. Huang, A. B. Kahng, S. Muddu, D. Stroobandt and D. Sylvester,
"Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design",
(.ps),
(.pdf),
((.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 2000,
pp. 5661.

F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky,
"Provably Good Global Buffering Using an Available Buffer Block Plan",
(.ps),
(.pdf),
((.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 2000,
pp. 104109.

Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky,
"Hierarchical Dummy Fill for Process Uniformity",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2001,
pp. 139144.

C. K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt,
"Toward Better Wireload Models in the Presence of Obstacles",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2001,
pp. 527532.

A. B. Kahng, S. Vaya and A. Zelikovsky,
"New Graph Bipartizations for DoubleExposure, Bright Field Alternating PhaseShift Mask Layout",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2001,
pp. 133138.

F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky,
"Provably Good Global Buffering by Multiterminal Multicommodity Flow Approximation",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2001,
pp. 120125.

A. B. Kahng,
"Design Technology Productivity in the DSM Era",
(.ps),
(.pdf),
invited paper,
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2001,
pp. 443448.

A. B. Kahng, S. Muddu, N. Pol and D. Vidhani,
"Noise Model for Multiple Segmented Coupled RC Interconnects",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality in Electronic Design ,
March 2001,
pp. 145150.

A. B. Kahng and S. Mantik,
"A System for Automatic Recording and Prediction of Design Quality Metrics",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality in Electronic Design,
March 2001,
pp. 8186.
(Best Paper Award).

C. K. Cheng, A. B. Kahng and B. Liu,
"Interconnect Implications of GrowthBased Structural Models for VLSI Circuits",
(.ps),
(.pdf),
(.ppt)
, Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
April 2001,
pp. 99106.

K. D. Boese, A. B. Kahng and S. Mantik,
"On the Relevance of Wire Load Models",
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
April 2001,
pp. 9198.

C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J. Sullivan and P. Villarrubia,
"Buffered Steiner Trees for Difficult Instances",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 2001,
pp. 49.

F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky,
"Practical Approximation Algorithms for Separable Packing Linear Programs",
(.ps),
(.pdf),
(.ppt),
Proc. 7th International Workshop on Algorithms and Data Structures,
August 2001,
pp. 325337.

C. Albrecht, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky,
"On the SkewBounded Minimum Buffer Routing Tree Problem",
(.ps),
(.pdf),
(.ppt),
Proc. The Tenth Workshop on Synthesis And System Integration of Mixed Technologies,
October 2001,
pp. 250256.

A. B. Kahng, R. Kastner, S. Mantik, M. Sarrafzadeh, and X. Yang,
"Studies of Timing Structural Properties for Early Evaluation of Circuit Design",
(.ps),
(.pdf),
(.ppt),
Proc. The Tenth Workshop on Synthesis and System Integration of Mixed Technologies,
October 2001,
pp. 285292.

C. J. Alpert, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky,
"MinimumBuffered Routing of NonCritical Nets for Slew Rate and Reliability Control",
(.ps),
(.pdf),
(.ppt), Proc. IEEEACM Intl. Conf. on
ComputerAided Design, November 2001,
pp. 408415.

C. Albrecht, A. B. Kahng, I. Mandoiu and A. Zelikovsky,
"Floorplan Evaluation with TimingDriven Global Wireplanning, Pin Assignment, and Buffer/Wire Sizing",
(.ps),
(.pdf),
(.ppt),
Proc. Intl. Conf. on VLSI Design/ASPDAC,
January 2002,
pp. 580587.
(Best Paper Award out of 269 submissions).

A. Kahng and S. Mantik,
"Measurement of Inherent Noise in EDA Tools",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality in Electronic Design,
March 2002,
pp. 206211.

A. Kahng and G. Smith,
"A New Design Cost Model for the 2001 ITRS",
(.ps),
(.pdf),
Proc. International Symposium on Quality Electronic Design,
March 2002,
pp. 190193.

Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky,
"MonteCarlo Methods for ChemicalMechanical Planarization on MultipleLayer and DualMaterial Models",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing,
Santa Clara, March 2002,
pp. 421432.

A. B. Kahng,
"DesignProcess Integration and Shared Red Bricks",
(.ps),
(.pdf),
Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, Santa Clara,
March 2002,
pp. 390400.

Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky,
"Closing the Smoothness and Uniformity Gap in Area Fill Synthesis",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 2002,
pp. 137142.

A. B. Kahng, S. Mantik and I. L. Markov,
"MinMax Placements for LargeScale Timing Optimization",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Symp. on
Physical Design,
April 2002,
pp. 143148.

A. B. Kahng,
"A Roadmap and Vision for Physical Design",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 2002,
pp. 112117.

C. Bandela, Y. Chen, A. B. Kahng, I. I. Mandoiu and A. Zelikovsky,
"Auctions with Buyer Preferences",
(.ps),
(.pdf),
Information Systems: The EBusiness Challenge  Proc. 17th IFIP World Computer Congress, Kluwer Academic Publishers,
2002,
pp. 221238.

Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang,
"Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI",
(.ps),
(.pdf),
Proc. IEEE ASIC/SoC Conference,
September 2002,
pp. 411415.

A. B. Kahng, I. I. Mandoiu, P. A. Pevzner, S. Reda, and A. Z. Zelikovsky,
"Border Length Minimization in DNA Array Design",
(.ps),
(.pdf),
(.ppt),
Proc. 2nd Workshop on Algorithms in Bioinformatics (WABI),
September 2002,
pp. 435448.

A. B. Kahng, B. Liu, and I. I. Mandoiu,
"NonTree Routing for Reliability and Yield Improvement",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 2002,
pp. 260266.

A. B. Kahng, I. I. Mandoiu, and A. Zelikovsky,
"Highly Scalable Algorithms for Rectilinear and Octilinear Steiner Trees",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2003,
pp. 827833.

P. Gupta, A. B. Kahng and S. Mantik,
"RoutingAware Scan Chain Ordering",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2003,
pp. 857862.

A. B. Kahng and B. Liu,
"QTree: A New Iterative Improvement Approach for Buffered Interconnect Optimization",
(.ps),
(.pdf),
Proc. IEEE Comp. Soc. Annual Symp. On VLSI,
Feb. 2003,
pp. 183188.

A. B. Kahng, R. Ellis, and Y. Zheng,
"Compression Algorithms for Dummy Fill VLSI Layout Data",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing,
Feb. 2003,
pp. 233245.

Y. Chen, P. Gupta, and A. B. Kahng,
"PerformanceImpact Limited Area Fill Synthesis",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing,
Feb. 2003,
pp. 7586.

D. Sylvester, P. Gupta, A. B. Kahng, and J. Yang,
"Toward PerformanceDriven Reduction of the Cost of RETBased Lithography Control" (Invited Paper)
(.ps),
(.pdf),
(.ppt),
Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing,
Feb. 2003,
pp. 123133.

S. V. Babin, A. B. Kahng, I. I. Mandoiu, and S. Muddu,
"Subfield Scheduling for Throughput Maximization in ElectronBeam Photomask Fabrication",
(.ps),
(.pdf),
(.ppt),
Emerging Lithographic Technologies VII, R. L. Engelstad (ed.), Proc. SPIE #5037,
Feb. 2003,
pp. 934942.

Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. H. Zheng,
"Area Fill Generation with Inherent Data Volume Reduction",
(.ps),
(.pdf),
(.ppt),
Proc. Design, Automation and Test in Europe,
March 2003,
pp. 868873.

P. Dasgupta, A. B. Kahng, and S. Muddu,
"A Novel Metric for Interconnect Architecture Performance",
(.ps),
(.pdf),
(.ppt),
Proc. Design, Automation and Test in Europe,
March 2003,
pp. 448453.

P. Gupta and A. B. Kahng,
"Quantifying Error in Dynamic Power Estimation of CMOS Circuits",
(.ps),
(.pdf),
(slides),
Proc. IEEE Intl. Symp. on Quality Electronic Design,
March 2003,
pp. 273278.

P. Gupta, A. B. Kahng and S. Mantik,
"A Proposal for RoutingBased TimingDriven Scan Chain Ordering",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE Intl. Symp. on Quality Electronic Design,
March 2003,
pp. 339343.

A. B. Kahng and I. L. Markov,
"Impact of Interoperability on CADIP Reuse: An Academic Viewpoint",
(.ps),
(.pdf),
Proc. IEEE Intl. Symp. on Quality Electronic Design,
March 2003,
pp. 208213.

H. Chen, C. K. Cheng, A. B. Kahng, I. Mandoiu and Q. Wang,
"Estimation of Wirelength Reduction for λGeometry vs. Manhattan Placement and Routing",
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
April 2003,
pp. 7176.

A. B. Kahng and X. Xu,
"Accurate PseudoConstructive Wirelength and Congestion Estimation",
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
April 2003,
pp. 6168.

A. B. Kahng,
"Research Directions for Coevolution of Rules and Routers",
(.ps),
(.pdf), invited paper,
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 2003,
pp. 122125.

A. B. Kahng and X. Xu,
"Local Unidirectional Bias for Smooth CutsizeDelay Tradeoff in PerformanceDriven Bipartitioning",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 2003,
pp. 8186.

A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky,
" Engineering a Scalable Placement Heuristic for DNA Probe Arrays",
(.ps),
(.pdf),
(.ppt),
Proc. Intl. Conf. on Research in Computational Molecular Biology,
apm:299oxAsrybEcM
April 2003,
pp. 148156.

S. V. Babin, A. B. Kahng, I. I. Mandoiu, and S. Muddu,
"Resist Heating Dependence on Subfield Scheduling in 50kV Electron Beam Maskmaking",
(.ps),
(.pdf),
(.ppt),
Photomask and NextGeneration Lithography Mask Technology X, Proc. SPIE #5130,
April 2003,
pp. 718726.

Y. Chen, P. Gupta and A. B. Kahng,
"PerformanceImpact Limited Area Fill Synthesis",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2003,
pp. 2227.

P. Gupta, A. B. Kahng, D. Sylvester and J. Yang,
"A CostDriven Lithographic Correction Methodology Based on OfftheShelf Sizing Tools",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2003,
pp. 1621.

H. Chen, C.K. Cheng, N.C. Chou, A. B. Kahng, J. F. MacDonald, P. Suaris, B. Yao and Z. Zhu,
"An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2003,
pp. 794799.

A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky,
"Design Flow Enhancements for DNA Arrays",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE Intl. Conf. on Computer Design,
October 2003,
pp. 116123.

P. Gupta, A. B. Kahng, I. I. Mandoiu, and P. Sharma,
"LayoutAware Scan Chain Synthesis for Improved Path Delay Fault Coverage",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 2003,
pp. 754759.

A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky,
"Evaluation of Placement Techniques for DNA Probe Array Layout",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 2003,
pp. 262269.

H. Chen, C. K. Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang, and B. Yao,
"The YArchitecture for OnChip Interconnect: Analysis and Methodology",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 2003,
pp. 1319.
 P. Gupta and A. B. Kahng,
"ManufacturingAware Physical Design",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM Intl. Conference on ComputerAided Design,
November 2003,
(embedded tutorial) pp. 681687.
 P. Gupta and A. B. Kahng,
"Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE Intl. Conf. on VLSI Design ,
Jan 2004,
pp. 431436.

H. Chen, C. K. Cheng, A. B. Kahng, M. Mori and Q. Wang,
"Optimal Planning for MeshBased Power Distribution",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2004,
pp. 444449.

A. B. Kahng and S. Reda,
"Combinatorial Group Testing Methods for the BIST Diagnosis Problem",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2004,
pp. 113116.

P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester,
"Investigation of Performance Metrics for Interconnect Stack Architectures",
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
Feb. 2004,
pp. 2329.

A. B. Kahng, I. Markov and S. Reda,
"Boosting: MinCut Placement with Improved Signal Delay",
(.ps),
(.pdf),
(.ppt),
Proc. Design, Automation and Test in Europe,
Feb. 2004,
pp. 10981103.

A. B. Kahng, I. I. Mandoiu, Q. Wang, X. Xu, and A. Zelikovsky,
"MultiProject Reticle Floorplanning and Wafer Dicing",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 2004,
pp. 7077.

A. B. Kahng, and Q. Wang,
"Implementation and Extensibility of an Analytic Placer",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 2004,
pp. 1825.

A. B. Kahng, I. L. Markov and S. Reda,
"On Legalization of RowBased Placements",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE GLSVLSI,
April 2004,
pp. 214219.

A. B. Kahng and S. Reda,
"Placement Feedback: A Concept and Method for Better MinCut Placements",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2004,
pp.357362.

P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester,
"Selective GateLength Biasing for CostEffective Runtime Leakage Control",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2004,
pp. 327330.

D. A. Antonelli, D. Z. Chen, T. J. Dysart, X. S. Hu, A. B. Kahng, P. M. Kogge, R. C. Murphy and M. T. Niemier,
"QuantumDot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2004,
pp. 363368.

L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang,
"Toward a Methodology for ManufacturabilityDriven Design Rule Exploration",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
June 2004,
pp. 311316.

A. B. Kahng, X. Xu and A. Zelikovsky,
"Yield and CostDriven Fracturing for Variable ShapedBeam Mask Writing",
(.ps),
(.pdf),
(.ppt),
Proc. 24th BACUS Symposium on Photomask Technology and Management,
September 2004,
pp. 360371.

P. Gupta, A. B. Kahng, C.H. Park, P. Sharma, D. Sylvester and J. Yang,
"Joining the Design and Mask Flows for Better and Cheaper Masks",
(.ps),
(.pdf),
(.ppt),
Proc. 24th BACUS Symposium on Photomask Technology and Management,
5567, 318 (2004).

L. He, A. B. Kahng, K. H. Tam and J. Xiong,
"VariabilityDriven Considerations in the Design of IntegratedCircuit Global Interconnects",
(.ps),
(.pdf),
(.ppt),
Proc. 21st Intl. VLSI Multilevel Interconnection (VMIC) Conf.,
September 2004,
pp. 214221.

A. B. Kahng, and S. Reda,
"Reticle Floorplanning With Guaranteed Yield for MultiProject Wafers",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on Computer Design,
October 2004,
pp. 106110.

A. B. Kahng, and Q. Wang,
"An Analytic Placer for MixedSize Placement and TimingDriven Placement",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
November 2004,
pp. 565572.

Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. Zheng,
"Evaluation of the New OASIS Format for Layout Fill Compression",
(.ps),
(.pdf),
(.ppt),
Proc. 11th IEEE Intl. Conf. on Electronics, Circuits and Systems,
December 2004,
pp. 377382.

P. Gupta, A. B. Kahng and C.H. Park,
"Detailed Placement for Improved Depth of Focus and CD Control",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
Jan. 2005,
pp. 343348.

P. Gupta, A. B. Kahng and C.H. Park,
"ManufacturingAware Design Methodology for Assist Feature Correctness",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing,
Feb. 2005,
pp. 131140.

C. Chiang, A. B. Kahng, S. Sinha, X. Xu, and A. Zelikovsky,
"Brightfield AAPSM Conflict Detection and Correction",
(.ps),
(.pdf),
(.ppt),
Proc. Design, Automation and Test in Europe,
March 2005,
pp. 908913.

P. Gupta, A. B. Kahng and P. Sharma,
"A Practical TransistorLevel Threshold Voltage Assignment Methodology",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE International Symposium on Quality Electronic Design,
March 2005,
pp. 261265.

P. Gupta, A.B. Kahng, D. Sylvester and J. Yang,
"PerformanceDriven OPC for Mask Cost Reduction",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE International Symposium on Quality Electronic Design,
March 2005,
pp. 270275.

L. He, A. B. Kahng, K. Tam and J. Xiong,
"Design of IC Interconnects with Accurate Modeling of CMP",
(.ps),
(.pdf),
(.ppt),
Proc. International Society for Optical Engineering (SPIE) Symposium on Microlithography,
5756, 109 (2005).

A. B. Kahng and S. Reda,
"Evaluation of Placer Suboptimality Via ZeroChange Netlist Transformations",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Physical Design,
April 2005,
pp 208215.

C. J. Alpert, A. B. Kahng, GJ. Nam, S. Reda and P. Villarrubia,
"A SemiPersistent Clustering Technique for VLSI Circuit Placement",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Physical Design,
April 2005,
pp. 200207.

L. He, A. B. Kahng, K. Tam and J. Xiong,
"Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Physical Design,
April 2005,
pp. 7885.

A. B. Kahng, S. Reda and Q. Wang,
"APlace: A General Analytic Placement Framework",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Physical Design,
April 2005,
pp. 233235.

P. Gupta, A. B. Kahng, C.H. Park, Kambiz Samadi and Xu Xu,
"Wafer TopographyAware Optical Proximity Correction for Better DOF Margin and CD Control",
(.ps),
(.pdf),
(.ppt),
Proc. Photomask and NextGeneration Lithography Mask Technology X,
April 2005,
pp. 844854.

P. Gupta, A. B. Kahng and C.H. Park,
"Improving OPC Quality Via Interactions Within the DesigntoManufacturing Flow",
(.ps),
(.pdf),
(.ppt),
Proc. Photomask and NextGeneration Lithography Mask Technology X,
April 2005,
pp. 131140.

Y.S. Cheon, P.H. Ho, A. B. Kahng, S. Reda and Q. Wang,
"PowerAware Placement",
(.ps),
(.pdf),
(.ppt),
Proc. Design Automation Conference,
June 2005,
pp. 795800.

P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester,
"SelfCompensating Design for Focus Variation",
(.ps),
(.pdf),
(.ppt),
Proc. Design Automation Conference,
June 1995,
pp. 365368.

A. B. Kahng, S. Muddu and P. Sharma,
"DefocusAware Leakage Estimation and Control",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Low Power Electronics and Design,
August 2005,
pp. 263268.

P. Gupta, A. B. Kahng and C.H. Park,
"Enhanced Resist and Etch CD Control by Design Perturbation",
(.ps),
(.pdf),
(.ppt),
Proc. 25th BACUS Symposium on Photomask Technology and Management,
5992, 59923P (2005).

P. Gupta, A. B. Kahng, S. Muddu, S. Nakagawa and C.H. Park,
"Modeling OPC Complexity for Design for Manufacturability",
(.ps),
(.pdf),
(.ppt),
Proc. 25th BACUS Symposium on Photomask Technology and Management,
5992, 59921W (2005).

A. B. Kahng, I. I. Mandoiu, X. Xu, and A. Zelikovsky,
"YieldDriven MultiProject Reticle Design and Wafer Dicing",
(.ps),
(.pdf),
(.ppt),
Proc. 25th BACUS Symposium on Photomask Technology and Management,
5992, 599249 (2005).
(1st place in Best Poster Awards and Best Paper Award)
(also appears in BACUS News March 2006, 22(3), pp. 110.)

A. B. Kahng, B. Liu and Q. Wang,
"Supply Voltage Degradation Aware Analytical Placement",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on Computer Design,
October 2005,
pp. 437443.
(Best Paper award; 5 awards out of 310 submissions)

P. Gupta, A. B. Kahng, O.S. Nakagawa and K. Samadi,
"Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing",
(.ps),
(.pdf),
(.ppt),
Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf.,
October 2005, pp. 352363.

A. B. Kahng and S. Reda,
"Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
November 2005,
pp. 173180.

C. Chiang, A. B. Kahng, S. Sinha and X. Xu,
"Fast and Efficient Phase Conflict Detection and Correction in StandardCell Layouts",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
November 2005,
pp. 149156.

A. B. Kahng, S. Reda and Q. Wang,
"Architecture and Details of a High Quality, LargeScale Analytical Placer",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
November 2005,
pp. 891898.
(Nominated for Best Paper award).

P. Gupta and A.B. Kahng,
"Efficient Design and Analysis of Robust Power Distribution Meshes",
(.ps),
(.pdf),
(.ppt),
Proc. International Conference on VLSI Design,
Jan. 2006,
pp. 337342.

A. B. Kahng, I. I. Mandoiu, X. Xu and A. Zelikovsky,
"MultiProject Reticle Design and Wafer Dicing under Uncertain Demand",
(.ps),
(.pdf),
(.ppt),
Proc. European Mask and Lithography Conference,
6281, 628104 (2006).
(Invited Paper).

P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah and P. Sharma,
"Lithography SimulationBased Fullchip Design Analyses",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing,
6156, 61560T (2006).

A. B. Kahng and R. O. Topaloglu,
"Generation of Design Guarantees for Interconnect Matching",
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
March 2006,
pp. 2934.

A. B. Kahng and S. Reda,
"A Tale of Two Nets: Studies of Wirelength Progression in Physical Design",
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
March 2006,
pp. 1724.

A. B. Kahng, B. Liu and X. Xu,
"Statistical Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation",
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
March 2006,
pp. 9197.

A. B. Kahng, C.H. Park, P. Sharma and Q. Wang,
"Lens Aberration Aware TimingDriven Placement",
(.ps),
(.pdf),
(.ppt),
Proc. Design, Automation and Test in Europe,
March 2006,
pp. 890895.

A. B. Kahng, K. Samadi and P. Sharma,
"Study of Floating Fill Impact on Interconnect Capacitance",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
April 2006,
pp. 691696.

A. B. Kahng, B. Liu and X. Xu,
"Constructing CurrentBased Gate Models Based on Existing Timing Library",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
April 2006,
pp. 3742.

A. B. Kahng, B. Liu and S. Tan,
"SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
April 2006,
pp. 638643.

A. B. Kahng, S. Muddu and P. Sharma,
"Impact of GateLength Biasing on ThresholdVoltage Selection",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
April 2006,
pp. 747754.

A. B. Kahng, B. Liu and S. Tan,
"Efficient Decoupling Capacitor Planning via Convex Programming Methods",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Symp. on Physical Design,
April 2006,
pp. 102107.
 A. B. Kahng and Q. Wang,
"A Faster Implementation of APlace",
(.ps),
(.pdf),
Proc. ACM/IEEE Intl. Symp. Physical Design,
2006,
pp. 218220. (Short Invited)

A. B. Kahng, X. Xu and A. Zelikovsky,
"Fast YieldDriven Fracture for Variable ShapedBeam Mask Writing",
(.ps),
(.pdf),
(.ppt),
Photomask and NextGeneration Lithography Mask Technology XI,
Proc. SPIE 6283, 62832R,
April 2006.

A. B. Kahng, B. Liu and X. Xu,
"Statistical Gate Delay Calculation with Crosstalk Alignment Consideration",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE GLSVLSI,
April 2006,
pp. 223228.

C. J. Alpert, A. B. Kahng, C. N. Sze and Q. Wang,
"TimingDriven Steiner Trees are (Practically) Free",
(.ps),
(.pdf),
(slides),
Proc. ACM/IEEE Design Automation Conference,
July 2006,
pp. 389392.

A. B. Kahng and C.H. Park,
"Auxiliary Pattern for CellBased OPC",
(.ps),
(.pdf),
(.ppt),
Proc. 27th BACUS Symposium on Photomask Technology and Management,
6349, 63494S (2006).

A. B. Kahng, C.H. Park and X. Xu,
"Fast DualGraph Based Hotspot Detection",
(.ps),
(.pdf),
(.ppt),
Proc. 27th BACUS Symposium on Photomask Technology and Management,
6281, 628104 (2006).

A. B. Kahng and X. Xu,
"A General Framework for MultiFlow, MultiLayer, MultiProject Reticles Design",
(.ps),
(.pdf),
(.ppt),
Proc. 27th BACUS Symposium on Photomask Technology and Management,
6349, 63494A (2006).
 A. Balasinski, J. Cetin, A. B. Kahng and X. Xu,
"A Procedure and Program to Calculate Shuttle Mask Advantage",
(.ps),
(.pdf),
(.ppt),
Proc. 27th BACUS Symposium on Photomask Technology and Management,
6349, 63492B (2006).
 A. B. Kahng and R. O. Topaloglu,
"Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction",
(.ps),
(.pdf),
(.ppt),
Proc. International Conference of Computer Design,
October 2006, pp. 222229.
 A. B. Kahng, P. Sharma, and A. Zelikovsky,
"Fill for Shallow Trench Isolation CMP",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
November 2006,
pp. 661668.
 J. Hu, A. B. Kahng, B. Liu, G. Venkataraman and X. Xu,
"A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
January 2007,
pp. 2431.
 A. B. Kahng and R. O. Topaloglu,
"A DOE Set for NormalizationBased Extraction of Fill Impact on Capacitances",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
March 2007,
pp. 467474.
(Best Paper award).
 A. B. Kahng, S. Reda and P. Sharma,
"OnLine Adjustable Buffering for Runtime Power Reduction",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
March 2007,
pp. 550555.
 A. B. Kahng, S. Muddu and P. Sharma,
"Detailed Placement for Leakage Reduction using Systematic ThroughPitch Variation",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Low Power Electronics and Design,
2007, pp. 110115.
 A. B. Kahng,
"Key Directions and a Roadmap for Electrical Design for Manufacturability",
(.ps),
(.pdf),
(.ppt),
Proc. European SolidState Circuits Conf.,
2007, pp. 8388.
(Invited Paper).
 A. B. Kahng and R. O. Topaloglu,
"PerformanceAware CMP Fill Pattern Optimization",
(.ps),
(.pdf),
(.ppt),
Proc. Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf.,
2007, pp. 135144.
(Invited Paper).
 A. B. Kahng, S.M Kang, W. Li and B. Liu,
"Analytical Thermal Placement for VLSI Lifetime Improvement and Minimum Performance Variation",
(.ps),
(.pdf),
(.ppt),
Proc. International Conference of Computer Design,
2007, pp. 7177.
 A. B. Kahng,
"Opportunities in Future Physical Implementation and Manufacturing Handoff Flows",
(.ps),
(.pdf),
(.ppt),
Proc. International SoC Design Conf.,
2007, pp. 4650.
(Invited Paper).
 A. B. Kahng, P. Sharma and R. O. Topaloglu,
"Exploiting STI Stress for Performance",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
2007, pp. 8390.
 P. Gupta, A. B. Kahng, Y. Kim, S. Shah, D. Sylvester,
"Investigation of Diffusion Rounding for PostLithography Analysis",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
2008, pp. 480485 .
 L. Carloni, A. B. Kahng, S. Muddu, A. Pinto, K. Samadi and P. Sharma,
"Interconnect Modeling for Improved SystemLevel Design Optimization",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
2008, pp. 258264.
 K. Jeong, A. B. Kahng and K. Samadi,
"Quantified Impacts of Guardband Reduction on Design Process Outcomes",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
2008, pp. 790897.
 P. Gupta, K. Jeong, A. B. Kahng and C.H. Park,
"Electrical Metrics for Lithographic LineEnd Tapering",
(.ps),
(.pdf),
(.ppt),
Proc. Photomask and NextGeneration Lithography Mask Technology,
2008, pp. 70238A1  70238A12.
 A. B. Kahng and S. Muddu,
"Predictive Modeling of LithographyInduced Linewidth Variation",
(.ps),
(.pdf),
(.ppt),
Proc. Photomask and NextGeneration Lithography Mask Technology,
2008, pp. 70280M1  70280M14
 K. Jeong, A. B. Kahng, C.H. Park and H. Yao,
"Dose Map and Placement CoOptimization for Timing Yield Enhancement and Leakage Power Reduction",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conference,
2008, pp. 516521.
 P. Gupta and A. B. Kahng,
"Bounded Lifetime Integrated Circuits",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conference,
2008, pp. 347348.
 R. J. Greenway, K. Jeong, A. B. Kahng, C.H. Park and J. S. Petersen,
"32nm 1D Regular Pitch SRAM Bitcell Design for InterferenceAssisted Lithography",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE BACUS Symposium on Photomask Technology and Management,
2008 7122, 71221L.
 A. B. Kahng, C.H. Park, X. Xu and H. Yao,
"Revisiting the Layout Decomposition Problem for Double Patterning Lithography",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE BACUS Symposium on Photomask Technology and Management,
2008 7122, 712221
 A. B. Kahng,
"Lithography and Design in Partnership: A New Roadmap",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE BACUS Symposium on Photomask Technology and Management,
2008 7122, 712202.
 A. B. Kahng, C.H. Park, X. Xu and H. Yao,
"Layout Decomposition for Double Patterning Lithography",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
2008, pp. 465472. (nominated for Best Paper award)
 A. B. Kahng, K. Samadi and R. O. Topaloglu,
"Recent Topics in CMPRelated IC Design for Manufacturing",
(.ps),
(.pdf),
(.ppt),
Proc. Materials Research Society,
2008.
 K. Jeong, A. B. Kahng and H. Yao,
"On Modeling and Sensitivity of Via Count in SOC Physical Implementation",
(.ps),
(.pdf),
(.ppt),
Proc. International SoC Design Conf.,
2008, pp. 125128.
(Invited Paper).
 A. B. Kahng and K. Samadi,
"Communication Modeling for SystemLevel Design",
(.ps),
(.pdf),
(.ppt),
Proc. International SoC Design Conf.,
2008, pp. 138143.
(Invited Paper).
 K. Jeong and A. B. Kahng,
"Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
2009, pp. 486491.
 K. Jeong, A. B. Kahng and H. Yao,
"Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
2009, pp. 127134.
 R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao and M. Smayling,
"Interference Assisted Lithography for Patterning of 1D Gridded Design",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE Symposium on Advanced Lithography,
2009 7271, 72712U.
 A. B. Kahng, B. Li, L.S. Peh and K. Samadi,
"ORION 2.0: A Fast and Accurate NoC Power and Area Model for EarlyStage Design Space Exploration",
(.ps),
(.pdf),
(.ppt),
Proc. Design, Automation and Test in Europe,
2009, pp. 423428.
 K. Jeong, A. B. Kahng and R. O. Topaloglu,
"Is Overlay Error More Important Than Interconnect Variations in Double Patterning?"
(.ps),
(.pdf),
(.ppt),
Proc. ACM International Workshop on SystemLevel Interconnect Prediction,
2009, pp. 310.
 A. Coskun, A. B. Kahng and T. S. Rosing,
"Temperature and CostAware Design of 3D Multiprocessor Architectures",
(.ps),
(.pdf),
(.ppt),
Proc. Euromicro DSD,
2009, pp. 183190.
 M. Gupta, K. Jeong and A. B. Kahng,
"Timing YieldAware Color Reassignment and Detailed
Placement Perturbation for Double Patterning Lithography"
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
2009, pp. 607614.
 K. Jeong and A. B. Kahng,
"A PowerConstrained MPU Roadmap for the International Technology Roadmap for Semiconductors (ITRS)",
(.ps),
(.pdf),
(.ppt),
Proc. International SoC Design Conf.,
2009, pp. 4952.
(Invited Paper).
 K. Jeong, A. B. Kahng and K. Samadi,
"ArchitecturalLevel Prediction of Interconnect Wirelength and Fanout",
(.ps),
(.pdf),
(.ppt),
Proc. International SoC Design Conf.,
2009, pp. 5356.
(Invited Paper).
 A. B. Kahng, S. Kang, R. Kumar and J. Sartori,
"Slack Redistribution for Graceful Degradation Under Voltage Overscaling",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
2010, pp. 825831.
 A. B. Kahng, B. Lin and K. Samadi,
"Improved OnChip Router Analytical Power and Area Modeling",
(.ps),
(.pdf),
(.ppt),
Proc. Asia and South Pacific Design Automation Conf.,
2010, pp. 241246.
 A. B. Kahng, S. Kang, R. Kumar and J. Sartori,
"Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on HighPerformance Computer Architecture,
2010, pp. 119129.
 K. Jeong, A. B. Kahng and R. O. Topaloglu,
"Assessing ChipLevel Impact of DoublePatterning Lithography",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
2010, pp. 122130.
 K. Jeong and A. B. Kahng,
"Methodology From Chaos in IC Implementation",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
2010, pp. 885892.
 K. Jeong, A. B. Kahng and S. Kang,
"Toward Effective Utilization of Timing Exceptions in Design Optimization",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Quality Electronic Design,
2010, pp. 5461.
 C.K. Cheng, A. B. Kahng, K. Samadi and A. Shayan,
"WorstCase Performance Prediction Under Supply Voltage and Temperature Variation",
(.ps),
(.pdf),
(.ppt),
Proc. SystemLevel Interconnect Prediction,
2010, pp. 9196.
 A. B. Kahng, S. Kang, R. Kumar and J. Sartori,
"RecoveryDriven Design: A Power Minimization Methodology for
ErrorTolerant Processor Modules",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conference,
2010, pp. 825830.
 P. Gupta, A. B. Kahng, A. Kasibhatla and P. Sharma,
"Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conference,
2010, pp. 597602.
 A. B. Kahng, B. Lin, K. Samadi and R. S Ramanujam,
"TraceDriven Optimization of NetworksonChip Configurations",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conference,
2010, pp. 437442.
 A. B. Kahng, B. Lin, K. Samadi and R. S Ramanujam,
"Efficient TraceDriven Metaheuristics for Optimization of NetworksonChip Configurations",
(.ps),
(.pdf),
(.ppt),
Proc. IEEE/ACM International Conference on ComputerAided Design,
2010, pp. 253263.
 C.K. Cheng, P. Du, A. B. Kahng, G. K. H. Pang, Y. Wang and N. Wong,
"More Realistic Power Grid Verification Based on Hierarchical Current and Power Constraints",
(.ps),
(.pdf),
(.ppt),
Proc. ACM Symp. on Physical Design.,
2011, pp. 159166.
 K. Jeong, A. B. Kahng and C. J. Progler,
"New YieldAware Mask Strategies",
(.ps),
(.pdf),
(.ppt),
Proc. Photomask and NextGeneration Lithography Mask Technology,
2011, pp. 80810P180810P12.
 K. Jeong and A. B. Kahng,
"Toward PDN Resource Estimation: A Law of Power Density",
(.ps),
(.pdf),
(.ppt),
Proc. SystemLevel Interconnect Prediction,
2011, pp. 16.
 S. K. Han, K. Jeong, A. B. Kahng and J. Lu,
"Stability and Scalability in Global Routing",
(.ps),
(.pdf),
(.ppt),
Proc. SystemLevel Interconnect Prediction,
2011, pp. 16.
 A. B. Kahng and V. Srinivas,
"Mobile System Considerations for SDRAM Interface Trends",
(.ps),
(.pdf),
(.ppt),
Proc. SystemLevel Interconnect Prediction,
2011, pp. 18.
 T.B. Chan, K. Jeong and A. B. Kahng,
"Performance and Variability Driven Guidelines for BEOL Layout Decomposition with LELE Double Patterning",
(.ps),
(.pdf),
(.ppt),
Proc. SPIE BACUS Symposium on Photomask Technology,
2011, 8166, 81663O181663O12.
 K. Jeong, A. B. Kahng, S. Kang, T. S. Rosing and R. Strong,
"MAPG: Memory Access Power Gating",
(.ps),
(.pdf),
(.ppt),
Proc. Design, Automation and Test in Europe,
2012, pp. 10541059.
 T.B. Chan, P. Gupta, A. B. Kahng and L. Lai,
"DDRO: A Novel Performance Monitoring Methodology Based on DesignDependent
Ring Oscillators",
(.ps),
(.pdf),
(.ppt),
Proc. Intl. Symposium on Quality Electronic Design,
2012, pp. 633640.
 T.B. Chan and A. B. Kahng,
"Improved Path Clustering for Adaptive PathDelay Testing",
(.ps),
(.pdf),
(.ppt),
Proc. Intl. Symposium on Quality Electronic Design,
2012, pp. 1320.
 C. K. Cheng, P. Du, A. B. Kahng and S. Weng,
"LowPower Gated Bus Synthesis for 3D IC via Rectilinear Shortestpath Steiner Graph",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Symp. Physical Design,
2012, pp. 105112.
 A. B. Kahng and S. Kang,
"Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Intl. Symp. Physical Design,
2012, pp. 153160.
 A. B. Kahng, B. Lin and S. Nath,
"Explicit Modeling of Control and Data for Improved NoC Router Estimation",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
2012,
pp. 392397
(nominated for Best Paper Award; 7 nominees out of 744 submissions).
 A. B. Kahng and S. Kang,
"AccuracyConfigurable Adder for Approximate Arithmetic Designs",
(.ps),
(.pdf),
(.ppt),
Proc. ACM/IEEE Design Automation Conf.,
2012,
pp. 820825.
 A. B. Kahng, S. Kang, T. S. Rosing and R. Strong,
"TAP  TokenBased Adaptive Power Gating",
(.ps),
(.pdf),
(.ppt),
Proc. International Symposium on Low Power Electronics and Design,
2012,
pp. 203208.
 J. Hu, A. B. Kahng, S. Kang, M. Kim and I. Markov,
"Sensitivityguided Metaheuristics for Accurate Discrete Gate Sizing",
(.pdf),
(.pptx),
Proc. IEEE/ACM International Conference on ComputerAided Design,
2012, pp. 233239.
 T.B. Chan and A. B. Kahng,
"Tunable Sensors for ProcessAware Voltage Scaling",
(.pdf),
(.pptx),
Proc. IEEE/ACM International Conference on ComputerAided Design,
2012, pp. 714.
 N. Jouppi, A. B. Kahng, N. Muralimanohar and V. Srinivas,
"CACTIIO: CACTI with Offchip PowerAreaTiming Models",
(.pdf),
(.pptx),
Proc. IEEE/ACM International Conference on ComputerAided Design,
2012, pp. 294301.
 T.B. Chan, A. B. Kahng, J. Li and S. Nath,
"Optimization of Overdrive Signoff",
(.pdf),
(.pptx),
Proc. Asia and South Pacific Design Automation Conf.,
2013, pp. 344  349.
 A. B. Kahng, S. Nath and T. S. Rosing,
"On Potential Design Impacts of Electromigration Awareness",
(.pdf),
(.pptx),
Proc. Asia and South Pacific Design Automation Conf.,
2013, pp. 527532.
 T.B. Chan and A. B. Kahng,
"PostRouting BackEndofLine Layout Optimization for Improved
TimeDependent Dielectric Breakdown Reliability",
(.pdf),
(.pptx),
Proc. SPIE Symposium on Advanced Lithography,
2013 8684, 86840L.
 T.B. Chan, W.T. J. Chan and A. B. Kahng,
"Impact of Adaptive Voltage Scaling on AgingAware Signoff",
(.pdf),
(.pptx),
Proc. Design, Automation and Test in Europe,
2013, pp. 16831688.
 A. B. Kahng, S. Kang and B. Park,
"ActiveMode Leakage Reduction with DataRetained Power Gating",
(.pdf),
(.pptx),
Proc. Design, Automation and Test in Europe,
2013, pp. 12091214.
 A. B. Kahng, B. Lin and S. Nath,
"Enhanced Metamodeling Techniques for HighDimensional IC Design
Estimation Problems",
(.pdf),
(.pptx),
Proc. Design, Automation and Test in Europe,
2013, pp. 18611866.
 T.B. Chan, A. B. Kahng and J. Li,
"ReliabilityConstrained Die Stacking Order in 3DICs under Manufacturing Variability",
(.pdf),
(.pptx),
Proc. International Symposium on Quality in Electronic Design ,
2013, pp. 1623.
 T.B. Chan, A. B. Kahng and J. Li,
"Toward Quantifying the IC Design Value of Interconnect Technology Improvements",
(.pdf),
(.pptx),
Proc. ACM/IEEE International Workshop on SystemLevel Interconnect Prediction,
2013.
 A. B. Kahng, S. Kang, H. Lee, S. Nath and J. Wadhwani,
"LearningBased Approximation of Interconnect Delay and Slew in Signoff Timing Tools",
(.pdf),
(.pptx),
Proc. ACM/IEEE International Workshop on SystemLevel Interconnect Prediction,
2013.
 A. B. Kahng, B. Lin and S. Nath,
"HighDimensional Metamodeling for Prediction of Clock Tree Synthesis Outcomes",
(.pdf),
(.pptx),
Proc. ACM/IEEE International Workshop on SystemLevel Interconnect Prediction,
2013.
 A. B. Kahng, S. Kang and H. Lee,
"Smart NonDefault Routing for Clock Power Reduction",
(.pdf),
(.pptx),
Proc. ACM/IEEE Design Automation Conf.,
2013.
 A. B. Kahng,
"The ITRS Design Technology and System Drivers Roadmap: Process and Status",
(.pdf),
(.pptx),
Proc. ACM/IEEE Design Automation Conf.,
2013. (Invited Paper)
 W.T. J. Chan, A. B. Kahng, S. Kang, R. Kumar and J. Sartori,
"Statistical Analysis and Modeling for Error Composition in Approximate Computation Circuits",
(.pdf),
(.pptx),
Proc. IEEE Intl. Conf. on Computer Design,
2013, pp. 4753.
 A. B. Kahng, S. Kang, H. Lee, I. L. Markov and P. Thapar,
"HighPerformance Gate Sizing with a Signoff Timer",
(.pdf),
(.pptx),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
2013, pp. 450457.
 A. B. Kahng, I. Kang and S. Nath,
"Incremental MultipleScan Chain Ordering for ECO FlipFlop Insertion",
(.pdf),
(.pptx),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design,
2013, pp. 705712.
 A. B. Kahng,
"LithographyInduced Limits to Scaling of Design Quality",
(.pdf),
Proc. DesignProcessTechnology Cooptimization for Manufacturability VIII (SPIE Microlithography Symposium),
2014, pp. 905302190530214. (Invited Paper)
 T.B. Chan, A. B. Kahng and J. Li,
"NOLO: A NoLoop, Predictive Useful Skew Methodology for Improved Timing in IC Implementation",
(.pdf),
(.pptx),
Proc. International Symposium on Quality in Electronic Design,
2014, pp. 504509.
 A. B. Kahng and H. Lee,
"Margin Recovery with Flexible FlipFlop Timing",
(.pdf),
(.pptx),
Proc. International Symposium on Quality Electronic Design,
2014, pp. 496503.
 A. B. Kahng and S. Nath,
"Optimal ReliabilityConstrained Overdrive Frequency Selection in Multicore Systems",
(.pdf),
(.pptx),
Proc. International Symposium on Quality Electronic Design,
2014, pp. 300308.
 A. B. Kahng and I. Kang,
"CoOptimization of Memory BIST Grouping, Test Scheduling, and Logic Placement",
(.pdf),
(.pptx),
Proc. Design, Automation and Test in Europe,
2014, pp. 196:1196:6.
 S. S. Han, A. B. Kahng, S. Nath and A. Vydyanathan,
"A Deep Learning Methodology to Proliferate Golden Signoff Timing",
(.pdf),
(.pptx),
Proc. Design, Automation and Test in Europe,
2014.
 G. Jerke and A. B. Kahng,
"Mission Profile Aware IC Design  A Case Study",
(.pdf),
(.pptx),
Proc. Design Automation and Test in Europe,
2014.
 A. B. Kahng, H. Lee and J. Li,
"Horizontal Benchmark Extension for Improved Assessment of Physical CAD Research",
(.pdf),
(.pptx),
Proc. Great Lakes Symposium on VLSI,
2014, pp. 2732.
 A. B. Kahng, S. Kang and J. Li,
"A New Methodology for Reduced Cost of Resilience",
(.pdf),
(.pptx),
Proc. Great Lakes Symposium on VLSI,
2014, pp. 157162.
 A. B. Kahng and H. Lee,
"Minimum Implant AreaAware Gate Sizing and Placement",
(.pdf),
(.pptx),
Proc. Great Lakes Symposium on VLSI,
2014, pp. 5762. (nominated for Best Paper award)
 T.B. Chan, K. Han, A. B. Kahng, J.G. Lee and S. Nath,
"OCVAware TopLevel Clock Tree Optimization",
(.pdf),
(.pptx),
Proc. Great Lakes Symposium on VLSI,
2014, pp. 3338.
 W.T. J. Chan, A. B. Kahng and S. Nath,
"Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling",
(.pdf),
(.pptx),
Proc. Proc. ACM/IEEE International Workshop on SystemLevel Interconnect Prediction, 2014, pp. 17.
 A. B. Kahng,
"Toward Holistic Modeling, Margining and Tolerance of IC Variability",
(.pdf),
(.pptx),
Proc. ISVLSI,
July 2014, pp. 284289. (Invited Paper)
 J.A. Carballo, W.T. J. Chan, P. A. Gargini, A. B. Kahng and S. Nath,
"ITRS 2.0: Toward a ReFraming of the Semiconductor Technology Roadmap",
(.pdf),
Proc. IEEE Intl. Conf. on Computer Design, 2014, pp. 139146.
 W.T. J. Chan, A. B. Kahng, S. Nath and I. Yamamoto,
"The ITRS MPU and SOC System Drivers: Calibration and
Implications for DesignBased Equivalent Scaling in the
Roadmap",
(.pdf),
(.pptx),
Proc. IEEE Intl. Conf. on Computer Design, 2014, pp. 153160.
 T.B. Chan, S. Dobre and A. B. Kahng,
"Improved Signoff Methodology with Tightened BEOL Corners",
(.pdf),
Proc. IEEE Intl. Conf. on Computer Design, 2014, pp. 311316.
 T.B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng and E. Sahouria,
"Benchmarking of Mask Fracturing Heuristics",
(.pdf),
(.pptx),
Proc. ACM/IEEE Intl. Conf. on ComputerAided Design, 2014, pp. 246253.
 Y. Chen, A. B. Kahng, B. Liu and W. Wang,
"CrosstalkAware Signal ProbabilityBased Dynamic Statistical Timing Analysis",
(.pdf),
Proc. International Symposium on Quality in Electronic Design, 2015, pp. 424429.
 S. Bang, K. Han, A. B. Kahng and V. Srinivas,
"Clock Clustering and IO Optimization for 3D Integration",
Proc. ACM/IEEE International Workshop on SystemLevel Interconnect Prediction,
(.pdf),
(.pptx),
2015.
 A. B. Kahng, M. Luo and S. Nath,
"SI for Free: Machine Learning of Interconnect Coupling Delay and Transition Effects",
(.pdf),
(.pptx),
Proc. ACM/IEEE International Workshop on SystemLevel Interconnect Prediction, 2015.
 M. Escalante, A. B. Kahng, M. Kishinevsky, U. Ogras and K. Samadi,
"MultiProduct Floorplan and Uncore Design Framework for Chip
Multiprocessors",
Proc. ACM/IEEE International Workshop on SystemLevel Interconnect Prediction,
(.pdf),
(.pptx),
2015.
 K. Han, A. B. Kahng, J. Lee, J. Li and S. Nath,
"A GlobalLocal Optimization Framework for Simultaneous MultiMode MultiCorner
Skew Variation Reduction",
(.pdf),
(.pptx),
Proc. ACM/IEEE Design Automation Conf., 2015.
 K. Han, A. B. Kahng and H. Lee,
"Evaluation of BEOL Design Rule Impacts Using an Optimal ILPBased Detailed Router",
(.pdf),
(.pptx),
Proc. ACM/IEEE Design Automation Conf., 2015.
 W.T. J. Chan, Y. Du, A. B. Kahng, S. Nath and K. Samadi,
"3DIC Benefit Estimation and Implementation Guidance from 2DIC Implementation",
(.pdf),
(.pptx),
Proc. ACM/IEEE Design Automation Conf., 2015.
 A. B. Kahng,
"New Game, New Goal Posts: A Recent History of Timing Closure",
(.pdf),
(.pptx),
Proc. ACM/IEEE Design Automation Conf., 2015. (Invited Paper)
 K. Han, A. B. Kahng, H. Lee and L. Wang,
"ILPBased CoOptimization of CutMask Layout, Dummy Fill and Timing for Sub14nm BEOL Technology",
(.pdf),
(.pptx),
Proc. 36th BACUS Symposium on Photomask Technology and Management, 2015. (nominated for
Best Paper award)
 K. Han, A. B. Kahng and H. Lee,
"Scalable Detailed Placement Legalization for Complex Sub14nm Constraints",
(.pdf),
(.pptx),
IEEE/ACM International Conference on ComputerAided Design, 2015.
 A. Alaghi, W.T. J. Chan, J. P. Hayes, A. B. Kahng and J. Li,
"Optimizing Stochastic Circuits for AccuracyEnergy Tradeoffs",
(.pdf),
(.pptx),
IEEE/ACM International Conference on ComputerAided Design, 2015.
 S. Dobre, A. B. Kahng and J. Li,
"Mixed CellHeight Implementation for Improved Design Quality in Advanced Nodes",
(.pdf),
(.pptx),
IEEE/ACM International Conference on ComputerAided Design, 2015.
 A. B. Kahng and F. Koushanfar,
"Evolving EDA Beyond its ERoots: An Overview",
(.pdf),
(.pptx),
IEEE/ACM International Conference on ComputerAided Design,
2015, pp. 247254. (Invited Paper)
 A. B. Kahng, M. Luo, G.J. Nam, S. Nath, D. Z. Pan and G. Robins,
"Toward Metrics of Design Automation Research Impact",
(.pdf),
(.pptx),
IEEE/ACM International Conference on ComputerAided Design,
2015, pp. 263270. (Invited Paper)
 S. Bang, K. Han, A. B. Kahng and M. Luo,
"Delay Uncertainty and Signal Criticality Driven Routing Channel
Optimization for Advanced DRAM Products",
(.pdf),
(.pptx),
Proc. Asia and South Pacific Design Automation Conf., 2016, pp. 697704.
 W.T. J. Chan, K. Y. Chung, A. B. Kahng, N. D. MacDonald and S. Nath,
"LearningBased Prediction of Embedded Memory Timing Failures During Initial
Floorplan Design",
(.pdf),
(.pptx),
Proc. Asia and South Pacific Design Automation Conf., 2016, pp. 178185.
 A. Coskun, A. Gu, W. Jin, A. J. Joshi, A. B. Kahng, J. Klamkin, Y. Ma,
J. Recchio, V. Srinivas and T. Zhang,
"CrossLayer Floorplan Optimization For Silicon Photonic NoCs In ManyCore
Systems",
(.pdf),
(.pptx),
Proc. Design, Automation and Test in Europe, 2016, pp. 13091314.
 K. Han, A. B. Kahng and J. Li,
"Improved Performance of 3DIC Implementations Through Inherent
Awareness of MixandMatch Die Stacking",
(.pdf),
(.pptx),
Proc. Design, Automation and Test in Europe, 2016, pp. 6166.
 W.T. J. Chan, A. B. Kahng and J. Li,
"Revisiting 3DIC Benefit with Multiple Tiers",
(.pdf),
(.pptx),
Proc. ACM/IEEE International Workshop on SystemLevel Interconnect Prediction, 2016, pp. 6:16:8.
 Kun Young Chung, A. B. Kahng and J. Li,
"Comprehensive Optimization of Scan Chain Timing During
LateStage IC Implementation",
(.pdf),
(.pptx),
Proc. ACM/IEEE Design Automation Conf., 2016, pp. 61:161:6.
 W.T. J. Chan, Y. Du, A. B. Kahng, S. Nath and K. Samadi,
"BEOL StackAware Routability Prediction from Placement Using Data Mining Techniques",
(.pdf),
(.pptx),
Proc. IEEE Intl. Conf. on Computer Design, 2016, pp. 4148.
 A. B. Kahng, J. Li and L. Wang,
"Improved Flop TrayBased Design Implementation for Power Reduction",
(.pdf),
(.pptx),
IEEE/ACM International Conference on ComputerAided Design, 2016, pp. 20:120:8. (nominated for Best Paper award)
 A. B. Kahng, H. Lee and J. Li,
"Measuring Progress and Value of IC Implementation Technology",
(.pdf),
(.pptx),
IEEE/ACM International Conference on ComputerAided Design, 2016, pp. 27:127:8. (Invited Paper)
 K. Blutman, H. Fatemi, A. B. Kahng, A. Kapoor, J. Li and J. Pineda de
Gyvez,
"Floorplan and Placement Methodology for Improved Energy Reduction
in Stacked PowerDomain Design",
(.pdf),
(.pptx),
Proc. Asia and South Pacific Design Automation Conf., 2017, pp. 444449.
 K. Han, A. B. Kahng, H. Lee and L. Wang,
"Performance and EnergyAware Optimization of BEOL Interconnect Stack Geometry in Advanced Technology Nodes",
(.pdf),
(.pptx),
Proc. Intl. Symp. on Quality in Electronic Design, 2017. (Invited Paper)
 W.T. J. Chan, P.H. Ho, A. B. Kahng and P. Saxena,
"Routability Optimization for Industrial Designs at Sub14nm Process Nodes Using Machine Learning",
(.pdf),
(.pptx),
Proc. ACM/IEEE Intl. Symp. on Physical Design, 2017, pp. 1521.
 P. Debacker, K. Han, A. B. Kahng, H. Lee, P. Raghavan and L. Wang,
"Vertical M1 RoutingAware Detailed Placement for Congestion and Wirelength Reduction in Sub10nm Nodes",
(.pdf),
(.pptx),
Proc. ACM/IEEE Design Automation Conf., 2017, pp. 51:151:6.
 T.B. Chan, W.T. J. Chan and A. B. Kahng,
"ILPBased Identification of Opportunistic Redundant Logic Insertions for Opportunistic Yield Improvement During Early Process Learning"
Proc. International Conference of Computer Design, 2017, to appear.
 C. Han, K. Han, A. B. Kahng, H. Lee, L. Wang and B. Xu,
"Optimal MultiRow Detailed Placement for Yield and ModelHardware Correlation Improvements in Sub10nm VLSI",
Proc. ACM/IEEE International Conference on ComputerAided Design, 2017, to appear.
