UCSD VLSI CAD LABORATORY














Last Modified: October 11, 2006
  1. The VLSI Design-Manufacturing Interface
    1. Layout Density Control for Improved VLSI Manufacturability
      Contact(s): Yu Chen (with Alex Zelikovsky)
    2. Image Compression Approaches for Area Fill Layout Data
      Contact(s): Yuhong Zheng, Robert Ellis
    3. Area Fill Compression by Hierarchical Rectangle Covering
      Contact(s): Parthasarathi Dasgupta, Ion Mandoiu (with Alex Zelikovsky)
    4. Phase-Shift Mask Layout Synthesis
      Contact(s): Alex Zelikovsky
    5. Alternative Mask Writing Strategies
      Contact(s): Swamy Muddu, Ion Mandoiu
    6. Manufacturing Variability
      Contact(s): Puneet Gupta

  2. VLSI Interconnect Performance Analysis and Optimization
    1. Estimates of Crosstalk-Induced Delay Variation.
      Contact(s): Puneet Gupta
    2. Layout-Based Solutions for Signal Integrity
      Contact(s): Puneet Gupta

  3. VLSI Interconnect Synthesis and Prediction
    1. Mapping Timing Constraints into Feasible Locations for Move-Based Placement
      Contact(s): Bao Liu
    2. Timing-Optimal Interconnect Synthesis.
      Contact(s): Bao Liu, Ion Mandoiu, Parthasarathi Dasgupta
    3. Buffered Interconnect Tree Synthesis for Signal Integrity Control
      Contact(s): Ion Mandoiu, Bao Liu (with Alex Zelikovsky)
    4. Buffer Planning, Global Routing, and Floorplan Evaluation
      Contact(s): Ion Mandoiu
    5. Interconnect Synthesis for Manufacturing Yield and Reliability Enhancement
      Contact(s): Bao Liu, Ion Mandoiu
    6. New Foundations of Interconnect Prediction
      Contact(s): Bao Liu
    7. Interconnect Prediction Considering Routing Obstacles
      Contact(s): Bao Liu

  4. Technology Extrapolation and the "Living Roadmap"
    Contact(s): Micheal Oliver


  5. MARCO GSRC Calibrating Achievable Design (C.A.D.) Theme
    1. The GTX system
      Contact(s): Micheal Oliver
    2. The GSRC Bookshelf for Fundamental CAD Algorithms
      Contact(s): Igor Markov
    3. A Metrics System for Design Process Measurement and Optimization
      Contact(s): Stefanus Mantik

  6. Other Topics

    1. Layout-Based Scan Optimizations
      Contact(s): Puneet Gupta
    2. DNA Array Synthesis
    3. Electronic / Computational Commerce
      Contact(s): Ion Mandoiu, Yu Chen (with Alex Zelikovsky)
    4. The Y Interconnect Architecture
      Contact(s): Ion Mandoiu, Qinke Wang (with Hongyu Chen,Bo Yao)
    5. Power Grid Planning
      Contact(s): Qinke Wang (with Hongyu Chen,Bo Yao)
    6. Mask Fabrication Cost Reduction
      Contact(s): Ion Mandoiu, Qinke Wang Xu Xu (with Alex Zelikovsky)