UCSD VLSI CAD LABORATORY














Last Modified: October 11, 2006
Presentations
  1. "Futures and Core Algorithm Technologies for Physical Design" Distinguished Lecture Talk, June 19, 1997.
  2. R. Brashears and A. B. Kahng, "Advanced routing for deep submicron technologies", May 1997.
  3. A. B. Kahng, A. E. Kennings, I. L. Markov, "Effective Optimization Strategies for Large-scale Placement", Sixth SIAM Conference on Optimization,Minisymposium on Optimization in Circuit Placement for VLSI , Atlanta, Georgia, May, 1999.
  4. A. E. Caldwell, A. B. Kahng and I. L. Markov, " CAD-IP Reuse via the Bookshelf for Fundamental VLSI CAD Algorithms", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 2000.
  5. D. Stroobandt, " GTX Update: Framework and New Studies", (.ps), (.pdf), Gigascale Silicon Research Center, June 2000.
  6. DAC99 Panels: Subwavelength Litho and EDA.
  7. ISPD00 Floorplanning Panel: Classical Floorplanning Harmful?
  8. SIA Strategic Technology Council presentation, January 24th, 2002.
  9. Michigan EECS Dept. VLSI Seminar talk, March 4th, 2002.
  10. A. B. Kahng, I. I. Mandoiu, P. A. Pevzner, S. Reda and A. Zelikovsky, "Border Length Minimization in DNA Array Design", (.ps), (.pdf), University of Georgia 2002 Research Symposium "Applying Bioinformatics: from Genes to Systems", October 4th, 2002.
  11. A. B. Kahng, "CAD Research, Pay now or Pay later ..." ICCAD Monday Evening Panel, November 2006.
  12. A. B. Kahng, "Futures at the Design-Manufacturing Interface", KAIST EE Department, Daejeon, Korea, March 28, 2011.
  13. A. B. Kahng, "The Future of Signoff", opening keynote, TAU-2011, Santa Barbara, CA, March 31, 2011.
  14. A. B. Kahng, "Energy Efficiency and Resilience in Future ICs", Yale University, April 25, 2011.
  15. A. B. Kahng, "Design-Based "Equivalent Scaling" to the Rescue of Moore's Law", University of California, Irvine, October 31, 2012.