
Last Modified: June 6, 2015
Many of the papers below have been made available in PDF format for easy access. Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.
Publications
Journal Papers

T. C. Hu and A. B. Kahng,
"All Trees Are Graceful (but some are more graceful than others)",
Applied Geometry and Discrete Mathematics
4 (1991), pp. 355358.

A. B. Kahng and G. Robins, "Optimal Algorithms for Extracting Spatial Regularity
in Images",
(.ps), (.pdf),
Pattern Recognition Letters 12 (1991), pp. 757764.

J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, "Provably
Good PerformanceDriven Global Routing",
(.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 11(6),
June 1992, pp. 739752.

A. B. Kahng and G. Robins, "A New Class of Iterative Steiner Tree Heuristics
with Good Performance",
(.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 11(7), July 1992, pp.
893902.

L. Hagen and A. B. Kahng, "New Spectral Methods for Ratio Cut Partitioning
and Clustering",
(.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 11(9), September 1992, pp. 10741085.

K. C. Chen, J. Cong, Y. Ding, A. B. Kahng and P. Trajmar, "DAGMAP: Graph
Based FPGA Technology Mapping For Delay Optimization",
(.ps), (.pdf),
IEEE Design and
Test, September 1992, pp. 720.

T. C. Hu, A. B. Kahng and G. Robins, "Solution of the Discrete Plateau
Problem",
(.ps), (.pdf),
Proc. National Academy of Sciences 89(10), October 1992,
pp. 92359236.

T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew
Clock Routing With Minimum Wirelength",
(.ps), (.pdf),
IEEE
Transactions on Circuits and Systems 39(11), November 1992, pp. 799814.

A. B. Kahng and G. Robins, "On Performance Bounds for a Class of Rectilinear
Steiner Tree Heuristics in Arbitrary Dimension",
(.ps), (.pdf),
IEEE Transactions on
ComputerAided Design of Integrated Circuits and Systems
11(11), November 1992, pp. 14621465.

J. Cong, A. B. Kahng and G. Robins, "MatchingBased Methods for HighPerformance
Clock Routing",
(.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 12(8), August 1993, pp. 11571169.

T. C. Hu, A. B. Kahng and G. Robins, "Optimal Robust Path Planning in General
Environments"
(.ps), (.pdf),
IEEE
Transactions on Robotics and Automation 9(6), December 1993, pp. 775784.

L. Hagen, A. B. Kahng, F. Kurdahi and C. Ramachandran, "On the Intrinsic
Rent Parameter and New SpectraBased Methods for Wireability Estimation"
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 13(1), January 1994, pp. 2737.

K. D. Boese and A. B. Kahng, "BestSoFar vs. WhereYouAre: Implications
for Optimal FiniteTime Annealing"
(.ps)
,
(.pdf), Systems
and Control Letters 22, January 1994, pp. 7178.

C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh, "On the
Minimum Density Interconnection Tree Problem"
(.ps), (.pdf), VLSI
Design 2(2) (1994), pp. 157169.

K. D. Boese, A. B. Kahng and S. Muddu, "New Adaptive Multistart Techniques
for Combinatorial Global Optimizations"
(.ps), (.pdf), Operations
Research Letters 16(2) (1994), pp. 101113. [second part]
(.ps)(.pdf)

T. C. Hu, A. B. Kahng and C. W. Tsao, "Old Bachelor Acceptance: A New Class
of NonMonotone Threshold Accepting Methods" (.ps)
,
(.pdf), ORSA
J. on Computing 7(4) (1995), pp. 417425.

K. D. Boese, A. B. Kahng, B. McCoy and G. Robins, "NearOptimal Critical
Sink Routing Tree Constructions"
(.ps)
,
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 14(12) (1995), pp. 14171436. (Nominated for Transactions
best paper award.)

C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng and D. Karger, "PrimDijkstra
Tradeoffs for Improved PerformanceDriven Global Routing"
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 14(7) (1995), pp. 890896.

C. J. Alpert and A. B. Kahng, "Recent Directions in Netlist Partitioning:
A Survey" (.ps)
,
(.pdf), Integration:
The VLSI Journal 19 (1995), pp. 181.

C. J. Alpert and A. B. Kahng, "MultiWay Partitioning Via Geometric Embeddings,
Orderings, and Dynamic Programming" (.ps)
,
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 14(11) (1995), pp. 13421358.

A. B. Kahng, G. Robins and E. A. Walkup, "Optimal Algorithms for Substrate
Testing in MultiChip Modules"
(.ps),
(.pdf), Intl.
J. on HighSpeed Electronics and Systems 6(4) (1995), pp. 595612.

A. B. Kahng and C. W. Tsao, "PlanarDME: A SingleLayer ZeroSkew Clock
Tree Router" (.ps)
,
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 15(1) (1996), pp. 819.

C. J. Alpert and A. B. Kahng, "A General Framework for Vertex Orderings,
With Applications to Circuit Clustering" (.ps),
(.pdf), IEEE
Transactions on Very Large Scale Integration (VLSI) Systems 4(2) (1996), pp. 240246.

C. J. Alpert and A. B. Kahng, "Splitting an Ordering into a Partition to
Minimize Diameter" (.ps),
(.pdf), J.
Classification 14 (1997), pp. 5174.

L. Hagen, J. H. Huang and A. B. Kahng, "On Implementation Choices for Iterative
Improvement Partitioning Algorithms" (.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 16(10) (1997), pp. 11991205.

Y. Cao, A. S. Fukunaga and A. B. Kahng, "Cooperative Mobile Robotics: Antecedents
and Directions" (.ps)
,
(.pdf), Autonomous
Robots 4(1) (1997), pp. 727.

A. B. Kahng and S. Muddu, "Analysis of RC Interconnections Under Ramp Input" (.ps),
(.pdf), ACM
Transactions on Design Automation of Electronic Systems 2(2), April 1997,
pp 168192.

A. B. Kahng and C.W. A. Tsao, "Practical BoundedSkew Clock Routing",(.ps),
(.pdf), J.
VLSI Signal Processing 16 (1997), pp. 199215.

I. Hong, A. B. Kahng and B. R. Moon, "Improved LargeStep Markov Chain
Variants for the Symmetric TSP", (.ps)
,
(.pdf), J.
Heuristics 3(1) (1997), pp. 6381.

L. Hagen and A. B. Kahng, "Combining Problem Reduction and Adaptive MultiStart:
A New Technique for Superior Iterative Partitioning",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 16(7) (1997), pp. 709717.

A. B. Kahng and S. Muddu, "An Analytical Delay Model for RLC Interconnects",
(.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 16(12) (1997), pp. 15071514.

J. Cong, A. B. Kahng, C. K. Koh and C.W. A. Tsao, "BoundedSkew Clock
and Steiner Routing",
(.ps),
(.pdf), ACM
Transactions on Design Automation of Electronic Systems 3(3) (1998), pp.
341388.

A. B. Kahng, G. Robins and E. A. Walkup, "How to Test a Tree",
(.pdf),
Networks 32 (1998), pp. 189197.

C. J. Alpert, J. H. Huang and A. B. Kahng, "Multilevel Circuit Partitioning",
(.ps),
(.pdf), IEEE
Transactions on ComputerAided Design of Integrated Circuits and Systems
17(8) (1998), pp. 655667.

J. Cong, A. B. Kahng and K. S. Leung, "Efficient
Algorithms for the Minimum ShortestPath Steiner Arborescence Problem With Applications
to VLSI Physical Design", (.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 17(1) (1998), pp. 2439.

C. J. Alpert, T. Chan, A. B. Kahng, I. Markov, P. Mulet, "Faster Minimization
of Linear Wirelength for Global Placement", (.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 17(1) (1998), pp. 313.

C. J. Alpert, A. B. Kahng and D. S. Yao, "Spectral Partitioning With Multiple
Eigenvectors",
(.ps),
(.pdf), Discrete
Applied Mathematics, 90 (1999), pp. 326. Selected for inclusion in
special volume, Discrete Applied Mathematics, Editors' Choice, Edition
1999.

A. B. Kahng, S. Muddu and E. Sarto, "Tuning Strategies for Global Interconnects
in HighPerformance DeepSubmicron ICs", (.ps),
(.pdf), VLSI
Design 10(1) (1999), pp. 2134.

C. J. Alpert, A. E. Caldwell, T. F. Chan, D. J.H. Huang, A. B. Kahng,
I. L. Markov and M. S. Moroz, "Analytic Engines Are Unnecessary in TopDown
PartitioningBased Placement", (.ps),
(.pdf), VLSI Design 10(1) (1999), pp. 99116.

A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky, "Filling Algorithms
and Analyses for Layout Density Control", (.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 18(4) (1999), pp. 445462.

A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky,
"On Wirelength Estimations for RowBased Placement", (.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 18(9), (1999), pp. 12651278.

P. Berman, A. B. Kahng, D. Vidhani, H. Wang and A. Zelikovsky, "Optimal
Phase Conflict Removal for Layout of Dark Field Alternating Phase Shifting
Masks",
(.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 19(2) (2000), pp. 175187.

C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov, "Hypergraph
Partitioning With Fixed Vertices", (.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 19(2) (2000), pp. 267272.

A. E. Caldwell, A. B. Kahng and I. L. Markov, "Iterative Partitioning With
Varying Node Weights", (.ps),
(.pdf), VLSI
Design 11(3) (2000), pp. 249258.

A. E. Caldwell, A. B. Kahng and I. L. Markov, "Design and Implementation
of MoveBased Heuristics for VLSI Hypergraph Partitioning", (.ps),
(.pdf), ACM
Journal of Experimental Algorithms 5 (2000).

A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal Partitioners and
Endcase Placers for Standardcell Layout",
(.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 19(11) (2000), pp. 13041313.

A. E. Caldwell, A. B. Kahng and I. L. Markov, "Toward CADIP Reuse: The
MARCO GSRC Bookshelf of Fundamental CAD Algorithms", (.ps), (.pdf),
IEEE Design and Test of Computers 19(3) (2002), pp. 7079.

A. B. Kahng, S. Mantik and D. Stroobandt, "Toward Accurate Models of Achievable
Routing", (.ps),
(.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 20(5) (2001), pp. 648659.

R. Baldick, A. B. Kahng, A. A. Kennings and I. L. Markov, "Efficient Optimization
by Modifying the Objective Function",
(.ps),
(.pdf), IEEE
Transactions on Circuits and Systems 48(8) (2001), pp. 947957.
 A. B. Kahng, J. Lach, W. H. MangioneSmith, S. Mantik, I. L. Markov,
M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, "ConstraintBased
Watermarking Techniques for Design Intellectual Property
Protection", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 20(10) (2001), pp.
12361252.

C.K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt, "Toward Better Wireload
Models in the Presence of Obstacles", (.ps),
(.pdf),
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(2) (2002), pp. 177188.
 R. E. Bryant, K. T. Cheng, A. B. Kahng, K. Keutzer, W. Maly, R.
Newton, L. Pileggi, J. M. Rabaey and A. SangiovanniVincentelli,
"Limitations and Challenges of CAD Technology for CMOS
VLSI", (.ps), (.pdf),
Proc. of IEEE 89(3) (2001), pp. 341365.

F. F. Dragan, A. B. Kahng, I. I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably
Good Global Buffering by Generalized Multiterminal Multicommodity Flow
Approximation", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 21(3) (2002), pp. 263274.

C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu,
S.T. Quay, S.S. Sapatnekar and A. J. Sullivan, "Buffered Steiner Trees for
Difficult Instances" (.ps), (.pdf), IEEE
Transactions on ComputerAided
Design 21(1) (2002), pp. 314.

A. Allan, D. Edenfeld, W. H. Joyner, A. B. Kahng, M. Rodgers
and Y. Zorian, "2001 Roadmap for Semiconductor Technology",
(.ps), (.pdf),
IEEE Computer, 35(1) (2002), pp. 4253.
 Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Area Fill
Synthesis for Uniform Layout Density", (.ps), (.pdf), IEEE Transactions on ComputerAided
Design 21(10) (2002), pp. 11321147.
 J. N. Cooper, R. B. Ellis and A. B. Kahng, "Asymmetric Binary Covering
Codes", (.ps), (.pdf), Journal of Combinatorial Theory, Series A
100(2) (2002), pp. 232249.
 C. Alpert, A. B. Kahng, B. Liu, I. I. Mandoiu and A. Zelikovsky,
"Minimum Buffered Routing with Bounded Capacitive Load for Slew Rate and
Reliability Control", (.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
22(3) (2003), pp. 241253.
 Y. Cao, C. Hu, X. Huang, A. B. Kahng, I. I. Markov, M. Oliver, D. Stroobandt and D. Sylvester, "Improved a
Priori Interconnect
Predictions and Technology Extrapolation in the GTX System", (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems
11(1) (2003), pp. 314.
 C. Albrecht, A. B. Kahng, B. Liu, I. I. Mandoiu and A. Zelikovsky,
"On the SkewBounded MinimumBuffer Routing Tree Problem", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
22(7) (2003), pp. 937945.
 A. E. Caldwell, A. B. Kahng and I. L. Markov, "Hierarchical Whitespace
Allocation in Topdown Placement", (.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 22(11) (2003), pp. 15501556.
 A. B. Kahng, B. Liu and I. I. Mandoiu, "Nontree Routing for Reliability and Yield Improvement", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 23(1) (2004), pp. 148156.
 D. Edenfeld, A. B. Kahng, M. Rodgers and Y. Zorian, "2003 Technology Roadmap for
Semiconductors", (.pdf)
IEEE Computer 37(1) (2004), pp. 4756.
 A. E. Caldwell, H.J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak, G. Qu and J. L. Wong, "Effective
Iterative Techniques for Fingerprinting Design IP", (.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 23(2) (2004), pp. 208215.
 A. B. Kahng, I. I. Mandoiu, P.A. Pevzner, S. Reda and A. Zelikovsky, "Scalable Heuristics for Design of DNA Probe
Arrays", (.ps), (.pdf) Journal of Computational Biology, 11(23) (2004), pp. 429447.
 A. B. Kahng and X. Xu, "Local Unidirectional Bias for CutsizeDelay Tradeoff in PerformanceDriven Bipartition", (.ps), (.pdf)
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 23(4) (2004), pp. 464471.
 A. B. Kahng and S. Reda, "Match Twice and Stitch: A New TSP Tour
Construction Heuristic", (.ps), (.pdf), Operations Research Letters, 2004, 32(6), pp. 499509.
As of February 2005, the most downloaded "hottest" article of Operations Research Letters: Science Direct (cached link).
 H. Chen, C. K. Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang and B. Yao, "The Yarchitecture for OnChip Interconnect: Analysis and Methodology", (.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 24(4) (2005), pp. 588599.
 P. Gupta, A. B. Kahng, I. I. Mandoiu and P. Sharma, "LayoutAware Scan Chain Synthesis for Improved Path Delay Fault Coverage", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 24(7) (2005), pp. 11041114.
 Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. Zheng, "Compressible Area Fill Synthesis", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 24(8) (2005), pp. 11691187.
 A. B. Kahng, and Q. Wang, "Implementation and Extensibility of an Analytic Placer",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 24(5) (2005), pp. 734747.
 P. Gupta, A. B. Kahng and S. Mantik, "RoutingAware Scan Chain Ordering", (.ps), (.pdf), ACM Transactions on Design Automation
of Electronic Systems 10(3) (2005), pp. 546560.
 A. B. Kahng and S. Reda, "New and Improved BIST Diagnosis Methods from Combinatorial Group Testing Theory",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 25 (3) (2006), pp. 533543.
 A. B. Kahng and S. Reda, "Wirelength Minimization for MinCut Placements via Placement Feedback",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 25(7) (2005), pp. 13011312.
 A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, "ComputerAided Optimization of DNA Array Design and Manufacturing",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 25 (2) (2006) 305320.
 S. Babin, A. B. Kahng, I. I. Mandoiu and S. Muddu, "Improving CD Accuracy and Throughput by Subfield Scheduling in Electron Beam Mask Writing", (.ps), (.pdf), Journal of Vacuum Science and Technology B 23(10) (2005), pp. 30943100.
 C. Alpert, A. Kahng, G.J. Nam, S. Reda and P. Villarrubia, "A Fast Hierarchical Quadratic Placement Algorithm",(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 25(4) (2006), pp. 678691.
 A. Kahng and S. Reda, "ZeroChange Netlist Transformations: A New Technique for Placement Benchmarking",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 25(12) (2006), pp. 28062819.
 P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, "GateLength Biasing for Runtime Leakage Control",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 25(8) (2006), pp. 14751485.
 P. Gupta, A. B. Kahng, C.H. Park, K. Samadi and X. Xu, "Wafer TopographyAware Optical Proximity Correction",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 25(12) (2006), pp. 27472756.
 C. Chiang, A. B. Kahng, S. Sinha, X. Xu and A. Zelikovsky, "Fast and Efficient BrightField AAPSM Conflict Detection and Correction",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 26(1) (2007), pp. 115126.
 A. B. Kahng, I. I. Mandoiu, X. Xu, and A. Zelikovsky, "Enhanced Design Flow and Optimizations for MultiProject Wafers",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 26(2) (2007), pp. 301311.
 P. Gupta, A. B. Kahng and C.H. Park, "Detailed Placement for Enhanced Control of Resist and Etch CDs",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 26(12) (2007), pp. 21442157.
 A. B. Kahng and K. Samadi, "CMP Fill Synthesis: A Survey of Recent Studies", (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 27(1) (2008), pp. 319.
 L. He, A. B. Kahng, K. H. Tam and J. Xiong, "Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 26(5) (2007), pp. 845857
 A. B. Kahng, B. Liu, and Q. Wang, "Stochastic Power/Ground Voltage Prediction and Optimization via Analytical Placement",
(.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(8) August 2007, pp. 904912
 A. B. Kahng, S. Muddu and P. Sharma, "DefocusAware Leakage Estimation and Control",(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 27(2) (2008), pp. 230240.
 A. B. Kahng, B. Liu and X. Xu, "Statistical Timing Analysis in the Presence of SignalIntegrity Effects", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 26(10) (2007), pp. 18731877.
 P. Gupta, A. B. Kahng, Y. Kim and D. Sylvester, "SelfCompensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 26(9) (2007), pp. 16141624.
 P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, "PerformanceDriven Optical Proximity Correction for Mask Cost Reduction", (.ps), (.pdf), SPIE J. Microlithography, Microfabrication and Microsystems 6 (2007).
 A. B. Kahng, S. Muddu and C.H. Park, "Auxiliary PatternBased OPC for Better Printability, Timing and Leakage Control", (.ps), (.pdf), SPIE J. Microlithography, Microfabrication and Microsystems 7(1) (2008), pp. 013002101300213.
 A. B. Kahng and R. O. Topaloglu, "DOEBased Extraction of CMP, Active and Via Fill Impact on Capacitances", (.ps), (.pdf), IEEE Transactions on Semiconductor Manufacturing 21(1) (2008), pp. 2232.
 A. B. Kahng, C.H. Park and X. Xu, "Fast DualGraphBased Hotspot Filtering", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 27(9) (2008), pp. 16351642.
 A. B. Kahng, P. Sharma and R. O. Topaloglu,
"Chip Optimization Through STIStressAware Placement Perturbations and Fill Insertion",
(.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 27(7) (2008), pp. 12411252.
 A. B. Kahng, C.H. Park, P. Sharma and Q. Wang,
"Lens Aberration Aware Placement for Timing Yield",
(.ps), (.pdf),
ACM Transactions on Design Automation of Electronic Systems 14(1) (2009), pp. 16:1  16:26.
 K. Jeong, A. B. Kahng and K. Samadi, "Impacts of Guardband Reduction on Design Process Outcomes: A Quantitative Approach", (.ps), (.pdf), IEEE Transactions on Semiconductor Manufacturing 22(4) (2009), pp. 552565.
 L. Carloni, A. B. Kahng, S. Muddu, A. Pinto, K. Samadi and P. Sharma, "Accurate Predictive Interconnect Modeling for SystemLevel Design",
(.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(4) (2010), pp. 679684.
 A. B. Kahng, C.H. Park, X. Xu and H. Yao, "Layout Decomposition Approaches for Double Patterning Lithography", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 29(6) (2010), pp. 939952.
 K. Jeong, A. B. Kahng, C.H. Park and H. Yao, "Dose Map and Placement CoOptimization for Improved Timing Yield and Leakage Power", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 29(7) (2010), pp. 10701082.
 M. Gupta, K. Jeong and A. B. Kahng, "Timing YieldAware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography", (.ps), (.pdf), IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 29(8) (2010), pp. 12291242.
 P. Gupta, K. Jeong, A. B. Kahng and C.H. Park, "Electrical Assessment of Lithographic Gate LineEnd Patterning", (.ps), (.pdf), SPIE J. Microlithography, Microfabrication and Microsystems 9(2) (2010), pp. 023014102301419.
 K. Jeong, A. B. Kahng, B. Lin and K. Samadi, "Accurate Machine LearningBased OnChip Router Modeling", (.ps), (.pdf), IEEE Embedded Systems Letters 2(3) (2010), pp. 6266.
 A. B. Kahng, B. Li, L.S. Peh and K. Samadi, "ORION 2.0: A PowerArea Simulator for Interconnection Networks", (.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20(1) (2012), pp. 191196.
 K. Jeong, A. B. Kahng and C. J. Progler, "CostDriven Mask Strategies Considering Parametric Yield, Defectivity and Production Volume”, (.ps), (.pdf),
SPIE J. Microlithography, Microfabrication and Microsystems 10(3) (2011), pp. 033021103302112.
 C.K. Cheng, P. Du, X. Hu, A. B. Kahng, G. K. H. Pang, Y. Wang and N. Wong, "A Realistic
EarlyStage Power Grid Verification Algorithm Based on Hierarchical Constraints", (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 31(3) (2012), pp. 109120.
(Correct author listing of this paper as given in Corrigendum, vol. 31(3) (2012), p. 452.)(Corrigendum)
 A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "RecoveryDriven Design:
Exploiting Error Resilience in Design of EnergyEfficient Processors",
(.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and
Systems 31(3) (2012), pp. 404417.
 A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "Enhancing the Efficiency
of EnergyConstrained DVFS Designs",
(.ps), (.pdf),
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems 21(10) (2013), pp. 17691782.
 A. B. Kahng, S. Kang, T. S. Rosing and R. Strong,
"ManyCore TokenBased Adaptive Power Gating",
(.ps), (.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 32(8) (2013), pp. 12881292.
 T.B. Chan, P. Gupta, A. B. Kahng and L. Lai, "Synthesis and Analysis of
DesignDependent Ring Oscillator (DDRO) Performance Monitors",
(.ps), (.pdf),
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22(10) (2013), pp. 21172130.
 T.B. Chan, W.T. J. Chan and A. B. Kahng,
"On AgingAware Signoff for Circuits with Adaptive Voltage Scaling",
(.ps), (.pdf),
IEEE Transactions on Circuits and Systems I (TCASI) 61(10) (2014), pp. 29202930.
 N. P. Jouppi, A. B. Kahng, N. Muralimanohar and V. Srinivas,
"CACTIIO: CACTI With OffChip PowerAreaTiming Models",
(.pdf),
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(7) (2015), pp. 12541267.
 T.B. Chan, A. B. Kahng, J. Li, S. Nath and B. Park,
"Optimization of Overdrive Signoff in HighPerformance and LowPower ICs",
(.pdf),
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(8) (2015), pp. 15521556.
 A. B. Kahng, B. Lin and S. Nath,
"ORION 3.0: A Comprehensive NoC Router Estimation Tool",
(.pdf),
IEEE Embedded Systems Letters 7(2) (2015), pp. 4145.
 A. B. Kahng, S. Kang, J. Li, and J. Pineda de Gyvez,
"An Improved Methodology for Resilient Design Implementation",
(.pdf),
ACM Transactions on Design Automation of Electronic Systems 20(4) (2015), pp. 66:166:26.
 V. K. De, A. B. Kahng, T. Karnik, B. Liu, M. Maleki and L. Wang,
"ApplicationSpecific CrossLayer Optimization Based on Predictive VariableLatency VLSI Design",
(.pdf),
ACM J. on Emerging Technologies in Computing Systems 12(3) (2015).
 T.B. Chan, P. Gupta, K. Han, A. A. Kagalwalla and A. B. Kahng,
"Benchmarking of Mask Fracturing Heuristics",
(.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 36(1) (2017), pp. 170183.
 J. L. Abellán, A. K. Coskun, A. Gu, W. Jin, A. Joshi, A. B. Kahng, J. Klamkin, C. Morales, J. Recchio, V. Srinivas and T. Zhang,
"Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation",
(.pdf),
IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems 36(5) (2017), pp. 801814.
 A. Alaghi, W.T. J. Chan, J. P. Hayes, A. B. Kahng and J. Li,
"Trading Accuracy for Energy in Stochastic Circuit Design",
(.pdf),
ACM Journal of Emerging Technologies in Computer Systems 13(3) (2017), pp. 47:147:30.
 W.T. J. Chan, A. B. Kahng and J. Li,
"Revisiting 3DIC Benefit with Multiple Tiers",
(.pdf),
Integration:
The VLSI Journal 58 (2017), pp.226235.
 P. Debacker, K. Han, A. B. Kahng, H. Lee, P. Raghavan and L. Wang,
"MILPBased Optimization of 2D Block Masks for
TimingAware Dummy Segment Removal in SelfAligned
Multiple Patterning Layouts",
(.pdf),
IEEE Transactions on ComputerAided Design of
Integrated Circuits and Systems 36(7) (2017), pp. 10751088.
 P. Agrawal, M. Broxterman, B. Chatterjee, P. Cuevas,
K. H. Hayashi, A. B. Kahng, P. K. Myana and S. Nath,
"Optimal Scheduling and Allocation for IC Design Management
and Cost Reduction",
(.pdf),
ACM Transactions on Design Automation of Electronic Systems 22(4) (2017), pp. 60:1pp.60:30.
 R. Balasubramonian, A. B. Kahng, N. Muralimanohar, A. Shafiee
and V. Srinivas, "CACTI 7: New Tools for Interconnect Exploration in
Innovative OffChip Memories",
(.pdf),
ACM Transactions on Architecture and Code Optimization 14(2)
(2017), pp.14:114:25.
 K. Blutman, H. Fatemi, A. Kapoor, A. B. Kahng, J. Li and J. Pineda de Gyvez,
"Logic Design Partitioning for Stacked Power Domains",
(.pdf),
IEEE Transactions on Very Large Scale Integration Systems 25(11) (2017), pp. 30453056.
 S. Dobre, A. B. Kahng and J. Li,
"Design Implementation with NonInteger MultipleHeight Cells for Improved Design Quality in Advanced Nodes",
(.pdf),
IEEE Transactions on ComputerAided Design of
Integrated Circuits and Systems 37(4) (2018), pp. 855868.
 A. Kahng, A. B. Kahng, H. Lee and J. Li,
"PROBE: Placement, Routing, BackEndofLine Measurement Utility",
(.pdf),
IEEE Transactions on ComputerAided Design of
Integrated Circuits and Systems 37(7) (2018), pp. 14591472.
 C.K. Cheng, A. B. Kahng, I. Kang and L. Wang,
"RePlAce: Advancing Solution Quality and Routability Validation in Global Placement",
IEEE Transactions on ComputerAided Design of
Integrated Circuits and Systems (2018), to appear.
 C. Han, A. B. Kahng, L. Wang and B. Xu,
"Enhanced Optimal MultiRow Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub10nm VLSI",
IEEE Transactions on ComputerAided Design of
Integrated Circuits and Systems (2018), to appear.
 K. Han, A. B. Kahng and J. Li,
"Optimal Generalized HTree Topology and Buffering for HighPerformance and LowPower Clock Distribution",
IEEE Transactions on ComputerAided Design of
Integrated Circuits and Systems (2018), to appear.
