UCSD VLSI CAD LABORATORY
Home

About Us
Faculty
Students
Staff
Alumni

Research
Overview
Projects
Advice
New Members

Publications
Books
Journals
Conferences
Columns
Reports

Presentations
Tutorials
Invited Talks

Resources
Our Library
Lit Search
Software Links
Useful Links

Sponsors

MARCO GSRC
Internal Pages
(password required)
Search VLSICAD



[Advanced Search]

Last Modified: November 9, 2023
Many of the papers below have been made available in PDF format for easy access. Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.
Publications
Journal Papers 
  1. T. C. Hu and A. B. Kahng, "All Trees Are Graceful (but some are more graceful than others)", Applied Geometry and Discrete Mathematics 4 (1991), pp. 355-358.
  2. A. B. Kahng and G. Robins, "Optimal Algorithms for Extracting Spatial Regularity in Images", (.ps), (.pdf), Pattern Recognition Letters 12 (1991), pp. 757-764. 
  3. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, "Provably Good Performance-Driven Global Routing", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11(6), June 1992, pp. 739-752.
  4. A. B. Kahng and G. Robins, "A New Class of Iterative Steiner Tree Heuristics with Good Performance", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11(7), July 1992, pp. 893-902. 
  5. L. Hagen and A. B. Kahng, "New Spectral Methods for Ratio Cut Partitioning and Clustering", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11(9), September 1992, pp. 1074-1085. 
  6. K. C. Chen, J. Cong, Y. Ding, A. B. Kahng and P. Trajmar, "DAG-MAP: Graph Based FPGA Technology Mapping For Delay Optimization", (.ps), (.pdf), IEEE Design and Test, September 1992, pp. 7-20. 
  7. T. C. Hu, A. B. Kahng and G. Robins, "Solution of the Discrete Plateau Problem", (.ps), (.pdf), Proc. National Academy of Sciences 89(10), October 1992, pp. 9235-9236. 
  8. T. H. Chao, Y. C. Hsu, J. M. Ho, K. D. Boese and A. B. Kahng, "Zero Skew Clock Routing With Minimum Wirelength", (.ps), (.pdf), IEEE Transactions on Circuits and Systems 39(11), November 1992, pp. 799-814. 
  9. A. B. Kahng and G. Robins, "On Performance Bounds for a Class of Rectilinear Steiner Tree Heuristics in Arbitrary Dimension", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11(11), November 1992, pp. 1462-1465. 
  10. J. Cong, A. B. Kahng and G. Robins, "Matching-Based Methods for High-Performance Clock Routing", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12(8), August 1993, pp. 1157-1169. 
  11. T. C. Hu, A. B. Kahng and G. Robins, "Optimal Robust Path Planning in General Environments" (.ps), (.pdf), IEEE Transactions on Robotics and Automation 9(6), December 1993, pp. 775-784. 
  12. L. Hagen, A. B. Kahng, F. Kurdahi and C. Ramachandran, "On the Intrinsic Rent Parameter and New Spectra-Based Methods for Wireability Estimation" (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13(1), January 1994, pp. 27-37. 
  13. K. D. Boese and A. B. Kahng, "Best-So-Far vs. Where-You-Are: Implications for Optimal Finite-Time Annealing" (.ps) , (.pdf), Systems and Control Letters 22, January 1994, pp. 71-78. 
  14. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh, "On the Minimum Density Interconnection Tree Problem" (.ps), (.pdf), VLSI Design 2(2) (1994), pp. 157-169. 
  15. K. D. Boese, A. B. Kahng and S. Muddu, "A New Adaptive Multistart Technique for Combinatorial Global Optimizations" (.pdf), Operations Research Letters 16(2) (1994), pp. 101-113.
  16. T. C. Hu, A. B. Kahng and C. W. Tsao, "Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting Methods" (.ps) , (.pdf), ORSA J. on Computing 7(4) (1995), pp. 417-425. 
  17. K. D. Boese, A. B. Kahng, B. McCoy and G. Robins, "Near-Optimal Critical Sink Routing Tree Constructions" (.ps) , (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14(12) (1995), pp. 1417-1436. (Nominated for Transactions best paper award.) 
  18. C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng and D. Karger, "Prim-Dijkstra Tradeoffs for Improved Performance-Driven Global Routing" (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14(7) (1995), pp. 890-896. 
  19. C. J. Alpert and A. B. Kahng, "Recent Directions in Netlist Partitioning: A Survey" (.ps) , (.pdf), Integration: The VLSI Journal 19 (1995), pp. 1-81. 
  20. C. J. Alpert and A. B. Kahng, "Multi-Way Partitioning Via Geometric Embeddings, Orderings, and Dynamic Programming" (.ps) , (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14(11) (1995), pp. 1342-1358. 
  21. A. B. Kahng, G. Robins and E. A. Walkup, "Optimal Algorithms for Substrate Testing in Multi-Chip Modules" (.ps), (.pdf), Intl. J. on High-Speed Electronics and Systems 6(4) (1995), pp. 595-612. 
  22. A. B. Kahng and C. W. Tsao, "Planar-DME: A Single-Layer Zero-Skew Clock Tree Router" (.ps) , (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 15(1) (1996), pp. 8-19. 
  23. C. J. Alpert and A. B. Kahng, "A General Framework for Vertex Orderings, With Applications to Circuit Clustering" (.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 4(2) (1996), pp. 240-246. 
  24. C. J. Alpert and A. B. Kahng, "Splitting an Ordering into a Partition to Minimize Diameter" (.ps), (.pdf), J. Classification 14 (1997), pp. 51-74. 
  25. L. Hagen, J. H. Huang and A. B. Kahng, "On Implementation Choices for Iterative Improvement Partitioning Algorithms" (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16(10) (1997), pp. 1199-1205. 
  26. Y. Cao, A. S. Fukunaga and A. B. Kahng, "Cooperative Mobile Robotics: Antecedents and Directions" (.ps) , (.pdf), Autonomous Robots 4(1) (1997), pp. 7-27. 
  27. A. B. Kahng and S. Muddu, "Analysis of RC Interconnections Under Ramp Input" (.ps), (.pdf), ACM Transactions on Design Automation of Electronic Systems 2(2), April 1997, pp 168-192. 
  28. A. B. Kahng and C.-W. A. Tsao, "Practical Bounded-Skew Clock Routing",(.ps), (.pdf), J. VLSI Signal Processing 16 (1997), pp. 199-215. 
  29. I. Hong, A. B. Kahng and B. R. Moon, "Improved Large-Step Markov Chain Variants for the Symmetric TSP", (.ps) , (.pdf), J. Heuristics 3(1) (1997), pp. 63-81. 
  30. L. Hagen and A. B. Kahng, "Combining Problem Reduction and Adaptive Multi-Start: A New Technique for Superior Iterative Partitioning", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16(7) (1997), pp. 709-717. 
  31. A. B. Kahng and S. Muddu, "An Analytical Delay Model for RLC Interconnects", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16(12) (1997), pp. 1507-1514. 
  32. J. Cong, A. B. Kahng, C. K. Koh and C.-W. A. Tsao, "Bounded-Skew Clock and Steiner Routing", (.ps), (.pdf), ACM Transactions on Design Automation of Electronic Systems 3(3) (1998), pp. 341-388.
  33. A. B. Kahng, G. Robins and E. A. Walkup, "How to Test a Tree", (.pdf), Networks 32 (1998), pp. 189-197.
  34. C. J. Alpert, J. H. Huang and A. B. Kahng, "Multilevel Circuit Partitioning", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(8) (1998), pp. 655-667.
  35. J. Cong, A. B. Kahng and K. S. Leung, "Efficient Algorithms for the Minimum Shortest-Path Steiner Arborescence Problem With Applications to VLSI Physical Design", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(1) (1998), pp. 24-39. 
  36. C. J. Alpert, T. Chan, A. B. Kahng, I. Markov, P. Mulet, "Faster Minimization of Linear Wirelength for Global Placement", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(1) (1998), pp. 3-13.
  37. C. J. Alpert, A. B. Kahng and D. S. Yao, "Spectral Partitioning With Multiple Eigenvectors", (.ps), (.pdf), Discrete Applied Mathematics, 90 (1999), pp. 3-26. Selected for inclusion in special volume, Discrete Applied Mathematics, Editors' Choice, Edition 1999.
  38. A. B. Kahng, S. Muddu and E. Sarto, "Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs", (.ps), (.pdf), VLSI Design 10(1) (1999), pp. 21-34.
  39. C. J. Alpert, A. E. Caldwell, T. F. Chan, D. J.-H. Huang, A. B. Kahng, I. L. Markov and M. S. Moroz, "Analytic Engines Are Unnecessary in Top-Down Partitioning-Based Placement", (.ps), (.pdf), VLSI Design 10(1) (1999), pp. 99-116. 
  40. A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky,  "Filling Algorithms and Analyses for Layout Density Control", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18(4) (1999), pp. 445-462.
  41. A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky,   "On Wirelength Estimations for Row-Based Placement", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 18(9), (1999), pp. 1265-1278.
  42. P. Berman, A. B. Kahng, D. Vidhani, H. Wang and A. Zelikovsky, "Optimal Phase Conflict Removal for Layout of Dark Field Alternating Phase Shifting Masks", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19(2) (2000), pp. 175-187.
  43. C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov, "Hypergraph Partitioning With Fixed Vertices", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19(2) (2000), pp. 267-272.
  44. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Iterative Partitioning With Varying Node Weights", (.ps), (.pdf), VLSI Design 11(3) (2000), pp. 249-258.
  45. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning", (.ps), (.pdf), ACM Journal of Experimental Algorithms 5 (2000).
  46. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal Partitioners and End-case Placers for Standard-cell Layout", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19(11) (2000), pp. 1304-1313.
  47. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Toward CAD-IP Reuse: The MARCO GSRC Bookshelf of Fundamental CAD Algorithms", (.ps), (.pdf), IEEE Design and Test of Computers 19(3) (2002), pp. 70-79.
  48. A. B. Kahng, S. Mantik and D. Stroobandt, "Toward Accurate Models of Achievable Routing", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20(5) (2001), pp. 648-659.
  49. R. Baldick, A. B. Kahng, A. A. Kennings and I. L. Markov, "Efficient Optimization by Modifying the Objective Function", (.ps), (.pdf), IEEE Transactions on Circuits and Systems 48(8) (2001), pp. 947-957.
  50. A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, "Constraint-Based Watermarking Techniques for Design Intellectual Property Protection", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20(10) (2001), pp. 1236-1252.
  51. C.-K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt, "Toward Better Wireload Models in the Presence of Obstacles", (.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 10(2) (2002), pp. 177-188.
  52. R. E. Bryant, K. T. Cheng, A. B. Kahng, K. Keutzer, W. Maly, R. Newton, L. Pileggi, J. M. Rabaey and A. Sangiovanni-Vincentelli, "Limitations and Challenges of CAD Technology for CMOS VLSI", (.ps), (.pdf), Proc. of IEEE 89(3) (2001), pp. 341-365.
  53. F. F. Dragan, A. B. Kahng, I. I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably Good Global Buffering by Generalized Multiterminal Multicommodity Flow Approximation", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21(3) (2002), pp. 263-274.
  54. C. J. Alpert, G. Gandham, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S.T. Quay, S.S. Sapatnekar and A. J. Sullivan, "Buffered Steiner Trees for Difficult Instances" (.ps), (.pdf), IEEE Transactions on Computer-Aided Design 21(1) (2002), pp. 3-14.
  55. A. Allan, D. Edenfeld, W. H. Joyner, A. B. Kahng, M. Rodgers and Y. Zorian, "2001 Roadmap for Semiconductor Technology", (.ps), (.pdf), IEEE Computer, 35(1) (2002), pp. 42-53.
  56. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Area Fill Synthesis for Uniform Layout Density", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design 21(10) (2002), pp. 1132-1147.
  57. J. N. Cooper, R. B. Ellis and A. B. Kahng, "Asymmetric Binary Covering Codes", (.ps), (.pdf), Journal of Combinatorial Theory, Series A 100(2) (2002), pp. 232-249.
  58. C. Alpert, A. B. Kahng, B. Liu, I. I. Mandoiu and A. Zelikovsky, "Minimum Buffered Routing with Bounded Capacitive Load for Slew Rate and Reliability Control", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(3) (2003), pp. 241-253.
  59. Y. Cao, C. Hu, X. Huang, A. B. Kahng, I. I. Markov, M. Oliver, D. Stroobandt and D. Sylvester, "Improved a Priori Interconnect Predictions and Technology Extrapolation in the GTX System", (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11(1) (2003), pp. 3-14.
  60. C. Albrecht, A. B. Kahng, B. Liu, I. I. Mandoiu and A. Zelikovsky, "On the Skew-Bounded Minimum-Buffer Routing Tree Problem", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(7) (2003), pp. 937-945.
  61. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Hierarchical Whitespace Allocation in Top-down Placement", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(11) (2003), pp. 1550-1556.
  62. A. B. Kahng, B. Liu and I. I. Mandoiu, "Non-tree Routing for Reliability and Yield Improvement", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(1) (2004), pp. 148-156.
  63. D. Edenfeld, A. B. Kahng, M. Rodgers and Y. Zorian, "2003 Technology Roadmap for Semiconductors", (.pdf) IEEE Computer 37(1) (2004), pp. 47-56.
  64. A. E. Caldwell, H.-J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak, G. Qu and J. L. Wong, "Effective Iterative Techniques for Fingerprinting Design IP", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(2) (2004), pp. 208-215.
  65. A. B. Kahng, I. I. Mandoiu, P.A. Pevzner, S. Reda and A. Zelikovsky, "Scalable Heuristics for Design of DNA Probe Arrays", (.ps), (.pdf) Journal of Computational Biology, 11(2-3) (2004), pp. 429-447.
  66. A. B. Kahng and X. Xu, "Local Unidirectional Bias for Cutsize-Delay Tradeoff in Performance-Driven Bipartition", (.ps), (.pdf) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(4) (2004), pp. 464-471.
  67. A. B. Kahng and S. Reda, "Match Twice and Stitch: A New TSP Tour Construction Heuristic", (.ps), (.pdf), Operations Research Letters, 2004, 32(6), pp. 499-509. As of February 2005, the most downloaded "hottest" article of Operations Research Letters: Science Direct (cached link).
  68. H. Chen, C. K. Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang and B. Yao, "The Y-architecture for On-Chip Interconnect: Analysis and Methodology", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(4) (2005), pp. 588-599.
  69. P. Gupta, A. B. Kahng, I. I. Mandoiu and P. Sharma, "Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(7) (2005), pp. 1104-1114.
  70. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. Zheng, "Compressible Area Fill Synthesis", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(8) (2005), pp. 1169-1187.
  71. A. B. Kahng, and Q. Wang, "Implementation and Extensibility of an Analytic Placer", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24(5) (2005), pp. 734-747.
  72. P. Gupta, A. B. Kahng and S. Mantik, "Routing-Aware Scan Chain Ordering", (.ps), (.pdf), ACM Transactions on Design Automation of Electronic Systems 10(3) (2005), pp. 546-560.
  73. A. B. Kahng and S. Reda, "New and Improved BIST Diagnosis Methods from Combinatorial Group Testing Theory", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 (3) (2006), pp. 533-543.
  74. A. B. Kahng and S. Reda, "Wirelength Minimization for Min-Cut Placements via Placement Feedback", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(7) (2005), pp. 1301-1312.
  75. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, "Computer-Aided Optimization of DNA Array Design and Manufacturing", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 (2) (2006) 305-320.
  76. S. Babin, A. B. Kahng, I. I. Mandoiu and S. Muddu, "Improving CD Accuracy and Throughput by Subfield Scheduling in Electron Beam Mask Writing", (.ps), (.pdf), Journal of Vacuum Science and Technology B 23(10) (2005), pp. 3094-3100.
  77. C. Alpert, A. Kahng, G.-J. Nam, S. Reda and P. Villarrubia, "A Fast Hierarchical Quadratic Placement Algorithm",(.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(4) (2006), pp. 678-691.
  78. A. Kahng and S. Reda, "Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(12) (2006), pp. 2806-2819.
  79. P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, "Gate-Length Biasing for Runtime Leakage Control", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(8) (2006), pp. 1475-1485.
  80. P. Gupta, A. B. Kahng, C.-H. Park, K. Samadi and X. Xu, "Wafer Topography-Aware Optical Proximity Correction", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(12) (2006), pp. 2747-2756.
  81. C. Chiang, A. B. Kahng, S. Sinha, X. Xu and A. Zelikovsky, "Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(1) (2007), pp. 115-126.
  82. A. B. Kahng, I. I. Mandoiu, X. Xu, and A. Zelikovsky, "Enhanced Design Flow and Optimizations for Multi-Project Wafers", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(2) (2007), pp. 301-311.
  83. P. Gupta, A. B. Kahng and C.-H. Park, "Detailed Placement for Enhanced Control of Resist and Etch CDs", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(12) (2007), pp. 2144-2157.
  84. A. B. Kahng and K. Samadi, "CMP Fill Synthesis: A Survey of Recent Studies", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(1) (2008), pp. 3-19.
  85. L. He, A. B. Kahng, K. H. Tam and J. Xiong, "Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(5) (2007), pp. 845-857
  86. A. B. Kahng, B. Liu, and Q. Wang, "Stochastic Power/Ground Voltage Prediction and Optimization via Analytical Placement", (.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15(8) August 2007, pp. 904-912
  87. A. B. Kahng, S. Muddu and P. Sharma, "Defocus-Aware Leakage Estimation and Control",(.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(2) (2008), pp. 230-240.
  88. A. B. Kahng, B. Liu and X. Xu, "Statistical Timing Analysis in the Presence of Signal-Integrity Effects", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(10) (2007), pp. 1873-1877.
  89. P. Gupta, A. B. Kahng, Y. Kim and D. Sylvester, "Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern Dependent Variation", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26(9) (2007), pp. 1614-1624.
  90. P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, "Performance-Driven Optical Proximity Correction for Mask Cost Reduction", (.ps), (.pdf), SPIE J. Microlithography, Microfabrication and Microsystems 6 (2007).
  91. A. B. Kahng, S. Muddu and C.-H. Park, "Auxiliary Pattern-Based OPC for Better Printability, Timing and Leakage Control", (.ps), (.pdf), SPIE J. Microlithography, Microfabrication and Microsystems 7(1) (2008), pp. 013002-1--013002-13.
  92. A. B. Kahng and R. O. Topaloglu, "DOE-Based Extraction of CMP, Active and Via Fill Impact on Capacitances", (.ps), (.pdf), IEEE Transactions on Semiconductor Manufacturing 21(1) (2008), pp. 22-32.
  93. A. B. Kahng, C.-H. Park and X. Xu, "Fast Dual-Graph-Based Hotspot Filtering", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(9) (2008), pp. 1635-1642.
  94. A. B. Kahng, P. Sharma and R. O. Topaloglu, "Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(7) (2008), pp. 1241-1252.
  95. A. B. Kahng, C.-H. Park, P. Sharma and Q. Wang, "Lens Aberration Aware Placement for Timing Yield", (.ps), (.pdf), ACM Transactions on Design Automation of Electronic Systems 14(1) (2009), pp. 16:1 - 16:26.
  96. K. Jeong, A. B. Kahng and K. Samadi, "Impacts of Guardband Reduction on Design Process Outcomes: A Quantitative Approach", (.ps), (.pdf), IEEE Transactions on Semiconductor Manufacturing 22(4) (2009), pp. 552-565.
  97. L. Carloni, A. B. Kahng, S. Muddu, A. Pinto, K. Samadi and P. Sharma, "Accurate Predictive Interconnect Modeling for System-Level Design", (.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(4) (2010), pp. 679-684.
  98. A. B. Kahng, C.-H. Park, X. Xu and H. Yao, "Layout Decomposition Approaches for Double Patterning Lithography", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(6) (2010), pp. 939-952.
  99. K. Jeong, A. B. Kahng, C.-H. Park and H. Yao, "Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(7) (2010), pp. 1070-1082.
  100. M. Gupta, K. Jeong and A. B. Kahng, "Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29(8) (2010), pp. 1229-1242.
  101. P. Gupta, K. Jeong, A. B. Kahng and C.-H. Park, "Electrical Assessment of Lithographic Gate Line-End Patterning", (.ps), (.pdf), SPIE J. Microlithography, Microfabrication and Microsystems 9(2) (2010), pp. 023014-1--023014-19.
  102. K. Jeong, A. B. Kahng, B. Lin and K. Samadi, "Accurate Machine Learning-Based On-Chip Router Modeling", (.ps), (.pdf), IEEE Embedded Systems Letters 2(3) (2010), pp. 62-66.
  103. A. B. Kahng, B. Li, L.-S. Peh and K. Samadi, "ORION 2.0: A Power-Area Simulator for Interconnection Networks", (.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20(1) (2012), pp. 191-196.
  104. K. Jeong, A. B. Kahng and C. J. Progler, "Cost-Driven Mask Strategies Considering Parametric Yield, Defectivity and Production Volume”, (.ps), (.pdf), SPIE J. Microlithography, Microfabrication and Microsystems 10(3) (2011), pp. 033021-1--033021-12.
  105. C.-K. Cheng, P. Du, X. Hu, A. B. Kahng, G. K. H. Pang, Y. Wang and N. Wong, "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(3) (2012), pp. 109-120. (Correct author listing of this paper as given in Corrigendum, vol. 31(3) (2012), p. 452.)(Corrigendum)
  106. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31(3) (2012), pp. 404-417.
  107. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "Enhancing the Efficiency of Energy-Constrained DVFS Designs", (.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21(10) (2013), pp. 1769-1782.
  108. A. B. Kahng, S. Kang, T. S. Rosing and R. Strong, "Many-Core Token-Based Adaptive Power Gating", (.ps), (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32(8) (2013), pp. 1288-1292.
  109. T.-B. Chan, P. Gupta, A. B. Kahng and L. Lai, "Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors", (.ps), (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22(10) (2013), pp. 2117-2130.
  110. T.-B. Chan, W.-T. J. Chan and A. B. Kahng, "On Aging-Aware Signoff for Circuits with Adaptive Voltage Scaling", (.ps), (.pdf), IEEE Transactions on Circuits and Systems I (TCAS-I) 61(10) (2014), pp. 2920-2930.
  111. N. P. Jouppi, A. B. Kahng, N. Muralimanohar and V. Srinivas, "CACTI-IO: CACTI With Off-Chip Power-Area-Timing Models", (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(7) (2015), pp. 1254-1267.
  112. T.-B. Chan, A. B. Kahng, J. Li, S. Nath and B. Park, "Optimization of Overdrive Signoff in High-Performance and Low-Power ICs", (.pdf), IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(8) (2015), pp. 1552-1556.
  113. A. B. Kahng, B. Lin and S. Nath, "ORION 3.0: A Comprehensive NoC Router Estimation Tool", (.pdf), IEEE Embedded Systems Letters 7(2) (2015), pp. 41-45.
  114. A. B. Kahng, S. Kang, J. Li, and J. Pineda de Gyvez, "An Improved Methodology for Resilient Design Implementation", (.pdf), ACM Transactions on Design Automation of Electronic Systems 20(4) (2015), pp. 66:1-66:26.
  115. V. K. De, A. B. Kahng, T. Karnik, B. Liu, M. Maleki and L. Wang, "Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design", (.pdf), ACM J. on Emerging Technologies in Computing Systems 12(3) (2015), pp. 21:1-21:19.
  116. T.-B. Chan, P. Gupta, K. Han, A. A. Kagalwalla and A. B. Kahng, "Benchmarking of Mask Fracturing Heuristics", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36(1) (2017), pp. 170-183.
  117. J. L. Abellán, A. K. Coskun, A. Gu, W. Jin, A. Joshi, A. B. Kahng, J. Klamkin, C. Morales, J. Recchio, V. Srinivas and T. Zhang, "Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36(5) (2017), pp. 801-814.
  118. A. Alaghi, W.-T. J. Chan, J. P. Hayes, A. B. Kahng and J. Li, "Trading Accuracy for Energy in Stochastic Circuit Design", (.pdf), ACM Journal of Emerging Technologies in Computer Systems 13(3) (2017), pp. 47:1-47:30.
  119. W.-T. J. Chan, A. B. Kahng and J. Li, "Revisiting 3DIC Benefit with Multiple Tiers", (.pdf), Integration: The VLSI Journal 58 (2017), pp. 226-235.
  120. P. Debacker, K. Han, A. B. Kahng, H. Lee, P. Raghavan and L. Wang, "MILP-Based Optimization of 2D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36(7) (2017), pp. 1075-1088.
  121. P. Agrawal, M. Broxterman, B. Chatterjee, P. Cuevas, K. H. Hayashi, A. B. Kahng, P. K. Myana and S. Nath, "Optimal Scheduling and Allocation for IC Design Management and Cost Reduction", (.pdf), ACM Transactions on Design Automation of Electronic Systems 22(4) (2017), pp. 60:1-pp.60:30.
  122. R. Balasubramonian, A. B. Kahng, N. Muralimanohar, A. Shafiee and V. Srinivas, "CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories", (.pdf), ACM Transactions on Architecture and Code Optimization 14(2) (2017), pp.14:1-14:25.
  123. K. Blutman, H. Fatemi, A. Kapoor, A. B. Kahng, J. Li and J. Pineda de Gyvez, "Logic Design Partitioning for Stacked Power Domains", (.pdf), IEEE Transactions on Very Large Scale Integration Systems 25(11) (2017), pp. 3045-3056.
  124. S. Dobre, A. B. Kahng and J. Li, "Design Implementation with Non-Integer Multiple-Height Cells for Improved Design Quality in Advanced Nodes", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37(4) (2018), pp. 855-868.
  125. A. Kahng, A. B. Kahng, H. Lee and J. Li, "PROBE: Placement, Routing, Back-End-of-Line Measurement Utility", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37(7) (2018), pp. 1459-1472.
  126. C.-K. Cheng, A. B. Kahng, I. Kang and L. Wang, "RePlAce: Advancing Solution Quality and Routability Validation in Global Placement", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38(9) (2019), pp. 1717-1730.
  127. C. Han, A. B. Kahng, L. Wang and B. Xu, "Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10nm VLSI", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38(9) (2019), pp. 1703-1716.
  128. K. Han, A. B. Kahng and J. Li, "Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39(2) (2020), pp. 478-491.
  129. H. Fatemi, A. B. Kahng, H. Lee, J. Li and J. Pineda de Gyvez, "Enhancing Sensitivity-Based Power Reduction for an Industry IC Design Context", (.pdf), Integration: The VLSI Journal 66 (2019), pp. 96-111.
  130. H. Fatemi, A. B. Kahng, H. Lee and J. Pineda de Gyvez, "Heuristic Methods for Fine-Grain Exploitation of FDSOI", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39(10) (2020), pp. 2860-2871.
  131. A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y. Ma, A. Narayan and V. Srinivas, "Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5D Systems", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39(12) (2020), pp. 5183-5196.
  132. M. Fogaça, A. B. Kahng, E. Monteiro, R. Reis, L. Wang and M. Woo, "On the Superiority of Modularity-Based Clustering for Determining Placement-Relevant Clusters", (.pdf) Integration: The VLSI Journal 74 (2020), pp. 32-44.
  133. A. B. Kahng, L. Wang and B. Xu, "TritonRoute: The Open Source Detailed Router", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40(3) (2021), pp. 547-559.
  134. A. B. Kahng, S. Kang, S. Kim and B. Xu, "Enhanced Power Delivery Pathfinding for Emerging 3D Integration Technology", (.pdf), IEEE Transactions on Very Large Scale Integration Systems 29(4) (2021), pp. 591-604.
  135. A. B. Kahng, J. Kuang, W.-H. Liu and B. Xu, "In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41(3) (2022), pp. 784-788.
  136. A. B. Kahng, L. Wang and B. Xu, "TritonRoute-WXL: The Open Source Router with Integrated DRC Engine", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41(4) (2022), pp. 1076-1089.
  137. C.-K. Cheng, A. B. Kahng, H. Kim, M. Kim, D. Lee, D. Park and M. Woo, "PROBE2.0: A Systematic Framework for Routability Assessment from Technology to Design in Advanced Nodes", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41(5) (2022), pp. 1495-1508.
  138. A. B. Kahng, "Machine Learning for CAD/EDA: The Road Ahead", (.pdf), IEEE Design & Test (2022) (Special Issue on Machine Learning for CAD/EDA), doi:10.1109/MDAT.2022.3161593.
  139. A. B. Kahng, M. Kim, S. Kim and M. Woo, "RosettaStone: Connecting the Past, Present and Future of Physical Design Research", (.pdf), IEEE Design & Test (2022), doi:10.1109/MDAT.2022.3179247.
  140. C.-K. Cheng, C. Holtz, A. B. Kahng, B. Lin, and U. Mallappa, "DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSIGraphs", (.pdf), ACM Transactions on Design Automation of Electronic Systems 28(4) (2023), pp. 52:1-31.
  141. V. A. Chhabria, W. Jiang, A. B. Kahng and S. Sapatnekar, "A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route", (.pdf), ACM Transactions on Design Automation of Electronic Systems 29(1) (2023), pp. 18:1-18:25.
  142. I. Bustany, A. B. Kahng, I. Koutis, B. Pramanik and Z. Wang, "K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 43(4) (2024), pp. 1232-1245.
  143. S. Choi, J. Jung, A. B. Kahng, M. Kim, C.-H. Park, B. Pramanik and D. Yoon, "PROBE3.0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement", (.pdf), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.
  144. A. B. Kahng, R. Varadarajan and Z. Wang, "Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-scale Complex IP Blocks", to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.
  145. A. B. Kahng, A. Mazumdar, J. Reeves and Y. Wang, "The TILOS AI Institute: Integrating Optimization and AI for Chip Design, Networks and Robotics", to appear in AI Magazine Special Issue for National AI Institutes, 2024.
  146. H. Esmaeilzadeh, S. Ghodrati, A. B. Kahng, J. K. Kim, S. Kinzer, S. Kundu, R. Mahapatra, S. D. Manasi, S. S. Sapatnekar, Z. Wang and Z. Zeng, "An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators", to appear in ACM Transactions on Design Automation of Electronic Systems, 2024.

maintained by webmaster@vlsicad.ucsd.edu