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Benchmark suite tests IC placement algorithms

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EE Times

SAN FRANCISCO, Calif. — A new suite of benchmarks that should help facilitate research in IC placement, floorplanning, and routing was put to the test in a placement contest at the International Symposium on Physical Design (ISPD) here Wednesday (April 6).

Winner of that contest was APlace, a general analytic placement engine developed at the University of California at San Diego. Second place went to mFar, a quadratic placer with a fixed-point addition from the University of California at Santa Barbara. Third place was shared by Dragon from the University of California at Los Angeles and mPL, also from UCLA.

More significant than the actual contest, however, is the new ISPD2005 benchmark suite itself, which is directly derived from industrial ASIC designs. It spans circuit sizes ranging from 210,000 to 2.1 million placeable objects, and preserves the physical structure of the designs, unlike previous suites.

The widely-used MCNC and ISPD98 benchmark suites have become "pretty outdated," said Gi-Joon Nam, ISPD placement context organizer and research staff member for IBM's Austin research laboratory. "We felt it was time to release real benchmarks that reflect real design constraints," he said. "It is pretty safe to say that these designs represent the real physical design challenges of today and tomorrow."

Nam said he was very impressed with all of the entries in the contest. "It was really obvious that APlace was the best placer this year in terms of wiring, and because it placed first in every single benchmark," he said.

While the placers in the contest come from the academic world, organizers said that commercial placement tools use much of the same technology. The contest, however, evaluated legality and wire length, not routability, which is a key concern for commercial placement tools.

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