- Panelists ponder challenges of 45 nm

Search Advanced Search
Newsletters | ACE Awards
Print Subscription | Print Edition

EE Times: Design News
Panelists ponder challenges of 45 nm

Print This Story Send As Email Discuss This Story
EE Times

SANTA CLARA, Calif. — The move to the 45 nm process node will be costly and challenging, but worth it for selected applications, according to panelists at the EDA Tech Forum here Thursday (Nov. 3).

Moderated by Wally Rhines, Mentor Graphics CEO, the panel was entitled "The road to 45 nm, a highway to hell?" But that wasn't the panel's conclusion. Despite steep design and fabrication costs, panelists were generally optimistic about the ability of EDA and foundry providers to come up with solutions, and of designers to leverage their investments in 45 nm technology through intellectual property (IP) reuse.

Jim Feldhan, president of Semico Research Corp., said there's a "short list" of potential products that will need 45 nm technology during its first few years. These include microprocessors, high-end graphics, memories, and any applications that need the transistor count and can drive high volumes. But with fabs costing perhaps $6 billion, he said, only a handful of companies will be able to build 45 nm fabs.

By 2012 or so, he said, 45 nm technology will be mature enough, and have enough design tool support, to attract a broader range of applications.

If there's an improvement in cost per function, "good things will happen at 45 nm," said John Martin, vice president for strategic alliances and partners at Chartered Semiconductor. But it's not cheap. He acknowledged that $2 million mask costs are "not out of the question," and said the major investment will be in the up-front design effort.

Ted Vucurevich, Cadence Design Systems CTO, agreed that 45 nm design costs will be very high. Because of issues like variability, verification, and growing software content, he said the cost of the "first gates" at 45 nm will be higher than at 65 nm. But Vucurevich said that designers will be able to leverage their investments through reusable architectures and IP, thus amortizing the cost across multiple products.

Vucurevich also said he is "very bullish" about the 45 nm mode opening up new opportunities for EDA vendors. In addition to design for manufacturability, he said that new tools will be needed for architectural design and verification.

The costs of 45 nm will raise the stakes, noted Martin. "To be successful, you have to be relatively certain of first pass success," he said. "This can be achieved through the diligent efforts of everyone in the tool chain."

Andrew Kahng, chairman and CTO of Blaze DFM, said that the "business organization" of EDA vendors hampers the development of solutions. He said the challenges of 45 nm design include density, leakage, and return on investment. Another challenge, he said, is "the aging mindsets like design rule manuals, or SP&R [synthesis, placement and routing] handoff to manufacturing. Those are really showing stress at 65 nm and probably won't survive the transition to 45 nm."

Kahng noted that manufacturing variability may cause excessive guardbanding and uncertainty. "We need to design around variability and understand what is easily modeled," he said. "We need to find systematic variation and pull it out and get rid of excessive guardbanding."

New transistors may also come into play at 45 nm, Martin noted. "There's an enormous effort with all kinds of new devices, and it's difficult to predict which one will supplant planar transistors. The vote is still open," he said.

Rhines asked panelists when the industry will move to statistical methods to combat variability.

"1979," replied Vucurevich. "As an old analog designer I'm laughing. Digital guys have come up with ways to hide all that stuff, but advanced design teams have been dealing with these issues since the 130 nm node. The real question is when we need to democratize the [statistical] technology for the rest of the design community. I think the answer is now."

EDA Tech Forums are held at various locations throughout the year. While sponsored by Mentor Graphics, the events are not restricted to Mentor customers.

Print This Story Send As Email Discuss This Story

eeProductCenter Launches SpecSearch®, New Parametric Parts Search Engine
In our continuing effort to enhance our site, eeProductCenter intorduces SpecSearch® powered by GlobalSpec. Click here.
  Free Subscription to EE Times
First Name   Last Name
Company Name   Title
Business Address   City

Email address  
  Electronics Marketplace
Free EDA, IP, and SoC, ASIC & FPGA design info
News, articles, tutorials, whitepapers, directories for EDA tools, IP, system-on-chip, ASIC and FPGA design from selected online sources. No registration required at

Free Membrane Switch Design Guide
Pannam Imaging with its ISO 9001 certification is the recognized leader in the design and manufacture of custom membrane switches. Our ISO systems assure the highest quality design and manufacturing as well as the best value

Free Timing Jitter Guide from Tektronix
Learn how to understand and characterize timing jitter with a complimentary Guide from Tektronix, provider of the most complete jitter measurement solutions.

Your Electronic Components Stock Stinks!
But if you email us your stock to we will post it for Free for over 3000 distributors to buy from you! Send us your stock list and your Electronic Components Stock SMELL willl be sold and not in your warehouse!

Trusted Communications and Embedded Supply Line
Speed up development cycles, cut costs and solve design issues with the Intel Communications Alliance, an extensive network of over 300 companies developing interoperable communications solutions.

Buy a link NOW:
  Design Resources
Fragmentation slows IPTV adoption
Though industry insiders agree that Internet Protocol TV is for real, the market today remains geographically fragmented by deployment type and by regional differences in digital-TV requirements.
More »

All White Papers »   



Platform Design: Better Signal Integrity with FPGAs

Accelerate. Innovate. Create the next generation network.

Keep up with the trends - the latest in Systems Architecture

NAND Flash gains the edge on the Memory Market. Read about it here.

Accelerate your design with Platform ASICs/Structured ASICs

  Sponsored Products

CommsDesign | | Design & Reuse | | Embedded Edge Magazine | Embedded Computing Solutions | Planet Analog | eeProductCenter | Electronics Supply & Manufacturing | Inside [DSP] | Automotive DesignLine | Power Management DesignLine | Wireless Net DesignLine | Video/Imaging DesignLine | Green SupplyLine | Industrial Control DesignLine | Network Systems DesignLine | Digital TV DesignLine | Programmable Logic DesignLine | Audio DesignLine | Mobile Handset DesignLine |TechOnLine
EE Times JAPAN | EE Times Asia | EE Times CHINA | EE Times FRANCE | EE Times GERMANY | EE Times Korea | EE Times Taiwan | EE Times UK
Electronics Express | Elektronik i Norden | Electronics Supply & Manufacturing - China | Microwave Engineering Europe
Career Center | Conference/Events | Custom Magazines | EE Times Info/Reader Service | GlobalSpec
NetSeminar Services | Sponsor Products | Subscribe to Print | Global Supply Chain Summit | Product Shopper