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April 27, 2002

Physical design needs an overhaul, speakers say

By Richard Goering
EE Times

April 9, 2002 (12:34 p.m. EST)

SAN DIEGO — Most of today's physical-design techniques for ICs are outdated and beset by artificial and unnecessary constraints, said Steven Teig, chief technology officer of Simplex Solutions Inc., in a provocative keynote Monday (April 8) at the International Symposium on Physical Design (ISPD) here. Teig joined a chorus of presenters who said that physical design is badly in need of an expanded focus, and called on EDA developers to think beyond yesterday's algorithms to tackle new problems such as leakage current, thermal issues and multiple on-chip voltage sources.

Many fundamental physical-design problems remain untouched by research, said Andrew Kahng, professor at the University of California at San Diego, who presented a "road map and vision" for IC physical design. "Physical design is not doing what we need it to do," he said.

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The ISPD 2002 program demonstrates the need to expand into new areas, said Massoud Pedram, ISPD technical-program chairman and professor at the University of Southern California. "People are paying attention to signal integrity, but it's not enough," he said.

Power plane integrity is also crucial, Pedram said, both from the standpoint of IR (voltage) drop and thermal gradients. He also noted that thermal variations across substrates and interconnects can have a big impact on physical design. One invited ISPD paper looked at thermal issues.

Pedram also noted the importance of leakage current, the topic of two invited papers. "Now, leakage current is 20 to 30 percent of total power dissipation. At 0.07 micron we expect it to rise to 40 or 50 percent," he said. Significant layout modifications may be needed to reduce that figure, he said.

The use of multiple on-chip voltages is another important trend, Pedram said. An invited ISPD paper discussed the impact of multiple voltages on physical design.

Scalability of conventional placement and routing was also a key topic. Researchers from the University of Bonn (Germany) received the ISPD "best paper" award for showing how congestion estimation can be incorporated into placement, thus improving routability.

Old techniques

In an animated, fast-moving keynote, Teig stressed the need for new algorithms and approaches. Well known as an IC physical-design pioneer, Teig has also developed automation systems for biological and chemical research, and he peppered his talk with references to biological and genetic systems.

Teig noted that computers today are a thousand times faster than they were in 1987, and yet designers are still using the same basic physical-design techniques, such as simulated annealing for placement, and rip-up and reroute gridded-maze autorouters. "It seems unlikely to me that this is the best we can do," he said.

Teig advocated the use of probabilistic tools and methodologies to better deal with process variations. He also called for more-automatic ways to optimize metrics. He discussed at some length the use of "joint probability distribution" models for combinational optimization techniques.

"If we can automate measurement design and pursue probabilistic design, we can build an infrastructure for 21st-century engineering," Teig said, noting that the same infrastructure can ultimately support engineered biological systems and nanotechnology.

Arguing that floor planning can't be done effectively without placement, Teig called for "floorplacers" that can manipulate various-size blocks and more than a million cells. He said clock, signal and power nets must all be routed together. Teig also called zero skew a "completely artificial constraint" and said that "intentional" skew, and slew, will help lower power requirements on chips.

One of Teig's more provocative questions was, "Do we need clocks?" He advocated semi-synchronous or totally asynchronous designs, and suggested that chip designers can learn from biological systems.

IC routing, said Teig, must be gridless and not constrained by directional preferences. A developer of Simplex's "X" architecture, Teig maintained it is "obvious" that diagonal wires will improve quality.

Teig offered a more detailed overview of the X architecture in an invited paper at the System Level Interconnect Prediction Workshop, a relatively new conference that immediately preceded ISPD.

Kahng of UC San Diego outlined requirements for physical design from the recent International Technology Roadmap for Semiconductors. But he noted that physical design represents only about one-sixth of the EDA industry, and that there aren't enough R&D people to solve critical problems such as analog layout synthesis and reuse, deep-submicron fault models, global signaling and synchronization, and process variability.

Presentations from ISPD papers are due to be posted at the ISPD 2002 Web site within several weeks.

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