ORION 2.0: A Power and Area Simulator for On-Chip Networks


Microprocessors are becoming increasingly interconnected. In the future, routers and links will be critical components of a microprocessor, alongside processors and memories. While the importance of low-power computing has been recognized, prior work has largely focused on the processing and memory elements of microprocessors, neglecting the communication components. This needs to be addressed, as on-chip networks consume a significant fraction of power in many-core chips.

ORION 2.0 is built to fill this need. It is a suite of dynamic and leakage power, and area models developed for various architectural components of on-chip networks, to enable rapid power-performance tradeoffs at the architecture and system levels.

Note: We released ORION3.0 for web download here


  • Kambiz Samadi
  • Bin Li
  • Prof. Andrew B. Kahng
  • Prof. Li-Shiuan Peh

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    Last updated: August 15, 2011