SWAMY MUDDU
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e-mail: swamy.muddu@gmail.com
mobile:  (858) 699 2983
url: http://vlsicad.ucsd.edu/~swamy
visa status: Indian Citizen on H1-B

OBJECTIVE:
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To seek a challenging position in ASIC Design (methodology and implementation), Design for Manufacturability (DFM) (methodology and implementation), or Computer-Aided Design (CAD) position that will effectively utilize the breadth of my acquired skills - research, design, and development to achieve design objectives.

PROFESSIONAL SUMMARY:
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* 5+ years of academic research experience for doctoral degree in VLSI physical design and DFM.
* 2+ years of industry experience in ASIC physical design and implementation, CAD, and automation for DFM.
* Strong understanding of DFM concepts - interaction between design layout, resolution enhancement techniques (RET), and lithography in sub-90nm technologies.
* Strong working knowledge of ASIC structural design - physical synthesis, physical implementation (place and route), timing / power ECOs, timing analysis / closure, physical verification, and DFM.
* Experienced with creation of physical verification (DRC / LVS) checkers from rules, optical proximity correction (OPC) and lithography simulation recipes.
* Experienced in test chip design / layout, design of experiments (DOE) and statistical modeling for DFM.
* Strong skills in setup of experimental ASIC design and lithography simulation flows, devising workarounds, and creating glue tools with code / scripts to create testbeds for research

TECHNICAL SKILLS:
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EDA Tools: Experience with ASIC Design, OPC, lithography simulation tools
* Cadence: BuildGates PKS, RTL Compiler, Conformal LowPower / LEC, SOC Encounter, QRC, VoltageStorm, Virtuoso
* Synopsys: Design Compiler, Astro, StarRCXT, PrimeTime SI, PrimePower, HSpice
* Mentor: Calibre DRC / LVS / RVE
* DFM Tools: Blaze MO, Calibre OPC / LithoSim / LFD (Litho-Friendly Design)
* OpenAccess: Strong development experience on OA (OpenAccess) API using C++ for design/stream (GDSII) data analysis / manipulation and interfacing to commercial EDA tools
* Scripting: Perl, Tcl, Sed, Awk, Csh
* DOE/Statistical Analysis: SAS JMP (DOE and data analysis), R, MATLAB
Languages: C, C++, Verilog

EDUCATION:
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Ph.D. in Electrical and Computer Engineering (2007)
University of California San Diego  *  La Jolla, CA
* Dissertation: Predictive Modeling of Integrated Circuit Manufacturing Variation
* Advisor: Professor Andrew B. Kahng

Bachelor of Engineering in Electronics and Communication Engineering (2001)
Osmania University  *  India (Graduated with Distinction)

PROFESSIONAL EXPERIENCE:
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Nextwave Semiconductor * San Diego, CA					        Dec 2007 - Present

Senior ASIC Design Engineer
Design automation, synthesis, low-power verification, low-power physical design methodology/ implementation, and design/manufacturability enhancement (DFM) of wireless SoC in 65nm.
* Developed scripted flows/utilities for automation of synthesis, place and route, leakage optimization, and physical verification (DRC / LVS) flows.
* Developed physical synthesis flows to obtain netlist with best QOR in terms of area/timing/power.  
* Provided feedback to designers for RTL changes for timing closure of critical paths.
* Developed timing/power optimization flows (in post-placement, post-CTS, and post-route phases).
* Developed redundant via insertion and wire-spreading flows to minimize the timing impact in post-route DFM-fix.  Analyzed the impact of dummy metal fill on post-route design timing.
* Member of a five-person team on physical implementation of a 10M gate low-power ASIC in 65nm.
* Block owner for two modules - Responsible for physical implementation: Placement, DFT / scan reordering, CTS, routing, extraction, leakage power optimization, and timing closure / signoff.
* Lead ECO effort (e.g., buffering, resizing) on top-level for DRV/setup/hold time fix and for leakage minimization (Vth swap) in post-route stage of design.
* Performed low-power verification (power shut-off/isolation, power/ground connectivity) on entire design using Cadence Common Power Format (CPF).  Developed checkers to traverse netlist hierarchy for isolation checks.
* Performed design planning - die size estimation, floorplanning, power planning of an integrated radio and baseband WiMax chipset.

Blaze DFM * Sunnyvale, CA							Jan 2005 - Jan 2006

R&D Intern / Engineer
Member of the start-up team involved with various tasks related to characterization and modeling for DFM, development, QOR testing, tapeout activities of reference test chips, and customer designs.
* Designed and developed a GDS2 annotation system to enable shaping of devices on wafer through OPC and lithography simulation tools (now a part of BlazeMO).
* Performed characterization and modeling of impact of OPC algorithm and tolerance settings on GDS2 shape complexity.
* Modeled the impact of systematic, process / lithography-induced variation on device shapes in standard cells.
* Developed OPC and litho simulation recipes to perform characterization.
* Developed test/regression suite to evaluate tool QOR. Composed test cases to evaluate QOR.
* Developed OA code to create test chips layouts (to characterize process variation).

RESEARCH EXPERIENCE:
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University of California San Diego * La Jolla, CA				    	Sep 2001 - Dec 2007
Graduate Student Researcher, VLSICAD Laboratory

Performed research on topics in DFM - Systematic process variation-aware design analyses, interactions between RET and design with emphasis on practical methodologies.  Co-authored 10 conference, five journal (in IEEE, ACM, and SPIE conference proceedings and journals), and one invention disclosure.
* Predictive Modeling of Lithography-Induced Linewidth Variation: Constructed models of device linewidth variation based on DOE and statistical modeling.
* Characterization of the Impact of Systematic Linewidth Variation on Timing: Characterized the impact of litho-induced linewidth variation on device linewidths in standard cells on timing.
* Detailed Placement for Leakage Reduction: Analyzed the impact of detailed placement on leakage induced by systematic linewidth variation.  Performed optimization of detailed placement to minimize leakage impact.
* Gate Length Biasing and Vth Interactions: Analyzed the impact of threshold voltage assignment to standard cells with the availability of gate length biased cell variants.
* Defocus-Aware Leakage Estimation/Control: Proposed the use of systematic, layout-induced topography impact on linewidth variation, and consequently, on leakage power.
* Performed research on other topics in: interconnect architecture performance evaluation, interconnect optimization for high-level design, mask writing optimization for improved variation. 
Detailed list of all research topics and publications available at : http://vlsicad.ucsd.edu/~swamy/research.php

AWARDS AND HONORS:
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* Recepient of "The Red-Eye Award" in recognition of a non-stop, three-month run toward a successful tape-out of WiMax SoC at Nextwave
* Mention in the list of contributors for the 2003 International Technology Roadmap for Semiconductors (ITRS) - http://public.itrs.net
* UCSD ECE Department Fellowship for 2001-2002
* Top of the class ('97-'01) in ECE Department, Osmania University, Hyderabad
* 2nd position in On-the-spot hardware design contest in IIT Roorkee TechFest (2001)

REFERENCES:
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* Available on request