Ph.D. Defense

• Manufacturing-Aware Physical Design Techniques [pdf]

Tutorials

• Leakage Components and Their Simulation [ppt]

Talks

• On-Line Adjustable Buffering for Runtime Power Reduction, ISQED07 [ppt]
• Fill for Shallow Trench Isolation CMP, ICCAD06 [ppt]
• Study of Floating Fill Impact on Interconnect Capacitance, ISQED06 [ppt]
• A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology, ISQED06 [ppt]
• Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control, DAC04 [ppt]
• Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage, ICCAD03 [ppt]

Posters

• Fill for Shallow Trench Isolation CMP, GSRC Annual Review 20006 [ppt]
• Online Adjustable Buffering for Runtime Power Reduction, UCSD Research Review 2006 [ppt]
• Lithography Simulation-Based Full-Chip Design Analyses, SPIE Microlithogarphy Conf. [ppt]
• Defocus-Aware Leakage Estimation and Control, UCSD Research Review 2005 [ppt]
• Gate-Length Biasing: A Highly Manufacturable Approach to Leakage Control, GSRC Annual Review 2004 [ppt]
• Gate-Length Biasing: A Highly Manufacturable Approach to Leakage Control, UCSD Research Review 2004 [ppt]
• Performance Counter Based Architecture Level Power Modeling, UCSD Research Review 2003 [ppt]
• Layout-Aware Scan-Based Delay Fault Testing, UCSD Research Review 2003 [ppt]