Biographical Data
Andrew B. Kahng (b. Oct. 1963, San Diego, CA) received the A.B. degree
in applied mathematics (physics) from Harvard College, and from June 1983
to June 1986 was affiliated with Burroughs Corporation Micro Components
Group in San Diego, where he worked in device physics, circuit simulation,
and CAD for VLSI layout. He received the M.S. and Ph.D. degrees in computer
science from the University of California at San Diego. He joined the
UCLA computer science department as an assistant professor in July 1989,
and became associate professor in July 1994 and full professor (at age 34)
in July 1998. From April 1996 through September 1997, he was on sabbatical
leave and leave of absence from UCLA, as Visiting Scientist at Cadence
Design Systems, Inc. He resumed his duties at UCLA in Fall 1997,
and from July 1998 to September 2000 served as the computer science
department's vice-chair for graduate studies. Effective January 1, 2001
Professor Kahng joined UCSD as Professor in the CSE and ECE Departments.
He served as Associate Chair of the UCSD CSE Department from 2003-2004.
In October 2004, Professor Kahng co-founded Blaze DFM, Inc., a Sunnyvale-based
EDA software company that delivers new cost and yield optimizations at the
IC design-manufacturing interface. He served as CTO of the company during
a two-year leave of absence, until returning to the university full-time in
September 2006.
Professor Kahng has published well over 300 journal and conference papers.
His Ph.D. graduates (Robins, Hagen, Boese, Alpert, Tsao, Muddu, Huang,
Markov, Liu, Chen, Mantik, Xu, Wang, Reda, Gupta, Sharma, Muddu) have gone
on to notable successes in both academia and industry.
He has received NSF Research Initiation and Young Investigator
awards, 11 Best Paper nominations, and 6 Best Paper awards (DAC, ISQED (2),
ICCD, ASP-DAC/VLSI Design, and BACUS). He was the founding General Chair
of the 1997 ACM/IEEE International Symposium on Physical
Design, co-founder of the ACM Workshop on System-Level Interconnect
Prediction, and defined the physical design roadmap as a member of
the Design Tools and Test technology working group (TWG) for the
1997, 1998 and 1999 renewals of the International Technology Roadmap
for Semiconductors (International
Technology Roadmap for Semiconductors). He has also served as a
member of the EDA Council's EDA 200X task force, which produced
this
report. He has been Chair of the U.S. Design Technology Working
Group, and of the Design International Technology Working Group, for
the 2001 renewal, 2002 update, and 2003 renewal of the
International Technology
Roadmap for Semiconductors.
He was Technical Program Chair of EDP-2001 (the workshop of the
Electronic Design Processes
Subcommittee of the IEEE DATC), and General Chair of EDP-2002.
He was also on the steering committees of ISPD-2001/2002 and
SLIP-2001. He is currently the Vice-Chair and Finance Chair of the
2008 Design Automation Conference, and remains on the committees of
ISPD, SLIP, and EDP. He served on the editorial boards of IEEE Transactions
on VLSI, IEEE Transactions on Circuits and Systems I, and IEEE Design and
Test (where he contributed the regular column, "The Road Ahead").
Professor Kahng's research interests include the VLSI design-manufacturing
interface, VLSI physical layout design and performance analysis, combinatorial
and graph algorithms, and stochastic global optimization. He also has broad
interests in other areas of applied algorithmics such as bioinformatics
or computational commerce.
Selected Honors
- National Science Foundation Young Investigator Award
- National Science Foundation Research Initiation Award
- First Place Award, Placement Contest (ACM International Symposium
on Physical Design 2005)
- 11 Best Paper Nominations (ACM/IEEE Design Automation Conference 1992,
1994; European Design Automation Conference 1992, 1994; Asia South-Pacific
Design Automation Conference 1999, 1999, 2002; IEEE ISQED 2001, 2007;
SPIE BACUS Symposium 2005; IEEE International Conference on Computer
Design 2005; IEEE International Conference on Computer-Aided Design 2005)
- Distinguished Paper Award (IEEE International Conference on CAD 1990)
- 6 Best Paper Awards (ACM/IEEE Design Automation Conference 1994,
IEEE International Symposium on Quality in Electronic Design
2001, Joint Asia and South Pacific Design Automation Conference and
International Conference on VLSI Design 2002, IEEE International Conference
on Computer Design 2005, SPIE BACUS Symposium 2005, IEEE International
Symposium on Quality in Electronic Design 2007)
Selected Professional Activities
- Chair, U.S. Design Technical Working Group and International
Design ITWG, International Technology Roadmap for Semiconductors,
2001 renewal, 2002 update, 2003 renewal.
- Technical Program Committee Co-Chair, ACM/IEEE Design Automation
Conference, June 2004. (Also Technical Program Committee member and
session organizer, 1995-2001, and Panels Subcommittee member, 1998-2002.)
- Technical Program Chair, IEEE DATC Electronic Design Processes
Workshop, April 2001 (and General Chair, EDP-2002, April 2002).
- General Co-Chair, Workshop on System-Level Interconnect
Prediction, April 1999; Technical Program Co-Chair, ACM International
Symposium on System-Level Interconnect Prediction, April 2000; Special
Sessions Chair and Steering Committee, SLIP-2001.
- Associate Editor, IEEE Transactions on VLSI Systems,
2003-present.
- Associate Editor, IEEE Transactions on Circuits and
Systems I, 2001-present.
- Guest Co-Editor, Special Issue on Roadmaps and Visions for
Design and Test, IEEE Design and Test ,
November-December 2001.
- Guest Co-Editor, Special Issue on System-Level Interconnect
Prediction, IEEE Trans. on VLSI Systems , 2000.
- Guest Co-Editor, Special Issue on Physical Design, IEEE
Trans. on CAD, April 1998.
- General Chair, ACM/IEEE International Symposium on Physical
Design, April 1997; Steering Committee, ISPD-2001; Program Committee,
ISPD-2004.
- Member, Design and Test Working Group (with responsibility for
Physical Design), 1997 and 1999 renewals, Semiconductor Industry
Association National Technology Roadmap for Semiconductors.
- Invited Session Organizer and Chair, INFORMS Annual Meeting,
May 1997.
- Technical Program Committee, Asia-Pacific Conference on Circuits
and Systems, November 1996.
- Associate Chair, VLSI Track; Panelist, CAD Track; Session
Organizer and Chair (Meta-heuristics in VLSI Layout), IEEE
International Symposium on Circuits and Systems, May 1996.
- Technical Committee, 3rd Canadian Workshop on Field-Programmable
Devices, April 1996.
- Tutorial Organizer/Presenter, ACM/IEEE
Design Automation Conference, June 1994, June 1999 and June 2002;
IEEE ICCAD November 1999 and November 2000; IEEE ASIC September 1998;
IEEE ISQED March 2000 and March 2001.
- Technical Committee, European Design Automation Conf.,
Paris, February 1994.
- Technical Program Committee, Session Chair and Co-Chair,
IEEE Intl. Conf. on Computer-Aided Design, Santa Clara,
CA, November 1993, November 1994, November 1995, November 1998, November 2000.
- Computer Science Fellowship Panel (one of five members),
National Defense Science and Engineering Graduate Fellowship Program, Feb. 1993.
- Technical Program Committee, Session Chair, 4th ACM/SIGDA Physical
Design Workshop, Lake Arrowhead, CA April 1993. Technical Program
Committee Chair, 5th ACM/SIGDA Physical Design Workshop, Reston, VA
April 1996.
- Expert Panel on Electromagnetic Detection
(organized by U.S. Army Research Office), Research
Triangle Park, NC, June 23-26, 1992.
- Technical Program Committee (Sub-Committee Chair),
Session Chair and Co-Chair,
5th and 6th IEEE Intl. Conf. on Application-Specific Integrated
Circuits, Rochester, NY, September 1992 and September 1993 (also Session
Chair and Co-Chair at 4th ASIC Conf. in 1991).
- Board of Editors, {\em J. Graph Algorithms and Applications}
and Intl. J. of High Speed Electronics and Systems.
- Ph.D. advisor for Gabriel Robins (IBM Fellowship, ACM Outstanding
Dissertation Award Nominee, NSF YI Award,
Packard Fellowship, Munster Chair, now at Univ. of Virginia CS Dept.);
Lars Hagen (IBM Fellowship, now at Cadence Design Systems, Inc.);
Kenneth D. Boese (GTE Fellowship, MICRO Fellowship, UCLA Dissertation
Year Fellowship, ACM Outstanding Dissertation Award Nominee, now at
Cadence Design Systems, Inc.);
Charles J. Alpert (DAC Scholarship, UCLA Dissertation Year
Fellowship, ACM Outstanding Dissertation Award Nominee, now at IBM
Austin Research Laboratory); Sudhakar Muddu (now at Sanera Systems,
Inc.); Chung-Wen Albert Tsao (DAC Scholarship, now at Cadence Design
Systems, Inc. (via Silicon Perspective Corp.));
Dennis Jen-Hsin Huang (now at Cadence Design Systems, Inc.
(via Silicon Perspective, Inc.)); Igor L. Markov
(now at Univ. of Michigan EECS Department); Bao Liu (now at
Incentia Design Systems, Inc.); and Yu Chen (now at UbiTech, Inc.).
- Reviewer for NSF, ARO, UC MICRO, numerous journals/conferences/symposia.
Miscellaneous Old Talks (beyond those under the
TALKS link)
- "Roadmaps Toward a Science of VLSI Design",
invited plenary talk, May 13, 1996, VLSI CAD Track,
IEEE Intl. Symposium on Circuits and Systems, Atlanta, May 1996.
- "Futures and Core Algorithm Technologies
for Physical Design", Distinguished Lecture Series,
June 19, 1997, Cadence Design Systems, Inc, San Jose CA.
- Futures for DSM Physical Implementation: Where is the Value,
and Who Will Pay?", keynote address , July 12, 2000,
12th Japan DA Show, Tokyo.
- Design Technology Productivity in the DSM Era, invited talk ,
February 2, 2001, Asia South-Pacific Design Automation Conference, Yokohama.