Andrew B. Kahng: Issued U.S. Patents

  1. A. B. Kahng and S. Muddu, "Diffusion-Based Method and Apparatus for Determining Circuit Interconnect Voltage Response", U. S. Patent No. 6,047,117, April 4, 2000.
  2. C. Albrecht, A. B. Kahng, I. I. Mandoiu and A. Z. Zelikovsky, "Floorplan Evaluation, Global Routing, and Buffer Insertion for Integrated Circuits", U. S. Patent No. 7,062,743, June 13, 2006.
  3. A. B. Kahng, P. Gupta, D. Sylvester and J. Yang, "Method for Correcting a Mask Design Layout", U. S. Patent No. 7,149,999, December 12, 2006.
  4. P. Gupta and A. B. Kahng, "Gate-Length Biasing for Digital Circuit Optimization", U. S. Patent No. 7,441,211, October 21, 2008.
  5. A. B. Kahng, P. Gupta, D. Sylvester and J. Yang, "Method for Correcting a Mask Design Layout", U. S. Patent No. 7,614,032, November 3, 2009.
  6. P. Gupta and A. B. Kahng, "System and Method for Varying the Starting Conditions for a Resolution Enhancement Program to Improve the Probability That Design Goals Will Be Met", U. S. Patent No. 7,627,849, December 1, 2009.
  7. P. Gupta, A. B. Kahng and C.-H. Park, "Method and System for Placing Layout Objects in a Standard-Cell Layout", U. S. Patent No. 7.640,522, December 29, 2009.
  8. O. S. Nakagawa, A. B. Kahng and P. Wong, "Layout Description Having Enhanced Fill Annotation", U. S. Patent No. 7,676,772, March 9, 2010.
  9. P. Gupta, A. Kahng and S. Shah, "Method and System for Integrated Circuit Optimization by Using an Optimized Standard-Cell Library", U. S. Patent No. 7,716,612, May 11, 2010.
  10. P. Gupta, A. B. Kahng and D. Reed, "Method and System for Reshaping a Transistor Gate in an Integrated Circuit to Achieve a Target Objective", U. S. Patent No. 7,730,432, June 1, 2010.
  11. P. Gupta and A. B. Kahng, "Method and System for Finding an Equivalent Circuit Representation for One or More Elements in an Integrated Circuit", U. S. Patent No. 7,743,349, June 22, 2010.
  12. O. S. Nakagawa, A. B. Kahng, P. Wong and P. Gupta, "Arrangement of Fill Unit Elements in an Integrated Circuit Interconnect Layer", U. S. Patent No. 7,745,239, June 29, 2010.
  13. P. Gupta and A. B. Kahng, "Method and System for Topography-Aware Reticle Enhancement", U. S. Patent No. 7,814,456, October 12, 2010.
  14. C. W. Moon, P. Gupta, P. J. Donehue and A. B. Kahng, "Method of Designing a Digital Circuit by Correlating Different Static Timing Analyzers", U. S. Patent No. 7,823,098, October 26, 2010.
  15. A. B. Kahng, P. Gupta and S. Shah, "System and Method for Performing Transistor-Level Static Performance Analysis Using Cell-Level Static Analysis Tools", U. S. Patent No. 7,865,856, January 4, 2011.
  16. A. B. Kahng and C.-H. Park, "Method, Apparatus and System for Designing an Integrated Circuit Including Generating At Least One Auxiliary Pattern for Cell-Based Optical Proximity Correction", U. S. Patent No. 7,873,929, January 18, 2011.
  17. A. B. Kahng, C.-H. Park and X. Xu, "Method and Apparatus for Detecting Lithographic Hotspots in a Circuit Layout", U. S. Patent No. 7,945,870, May 17, 2011.
  18. P. Gupta, A. B. Kahng, P. Sharma and S. Muddu, "Method and System for Wafer Topography-Aware Integrated Circuit Design Analysis and Optimization", U. S. Patent No. 8,024,675, September 20, 2011.
  19. J. Cox, A. B. Kahng and P. Sharma, "Internet Telephony Through Hosts", U. S. Patent No. 8,073,977, December 6, 2011.
  20. A. B. Kahng, P. Gupta, D. Sylvester and J. Yang, "Tool for Modifying Mask Design Layout", U. S. Patent No. 8,103,981, January 24, 2012.
  21. P. Gupta and A. B. Kahng, "Gate-Length Biasing for Digital Circuit Optimization", U. S. Patent No. 8,127,266, February 28, 2012.
  22. P. Gupta and A. B. Kahng, "Methods for Gate-Length Biasing Using Annotation Data", U. S. Patent No. 8,185,865, May 22, 2012.
  23. A. B. Kahng and H. Yao, "Layout Decomposition for Double Patterning Lithography", U.S. Patent No. 8,402,396, March 19, 2013.
  24. P. Gupta and A. B. Kahng, "Standard Cells Having Transistors Annotated for Gate-Length Biasing", U.S. Patent No. 8,490,043, July 16, 2013.
  25. P. Gupta and A. B. Kahng, "Standard Cells Having Transistors Annotated for Gate-Length Biasing", U.S. Patent No. 8,635,583, January 21, 2014.
  26. A. B. Kahng and H. Yao, "Layout Decomposition for Double Patterning Lithography", U.S. Patent No. 8,751,974, June 10, 2014.
  27. P. Gupta and A. B. Kahng, "Standard Cells Having Transistors Annotated for Gate-Length Biasing", U.S. Patent No. 8,756,555, June 17, 2014.
  28. P. Gupta and A. B. Kahng, "Standard Cells Having Transistors Annotated for Gate-Length Biasing", U.S. Patent No. 8,869,094, October 21, 2014.
  29. P. Gupta and A. B. Kahng, "Standard Cells Having Transistors Annotated for Gate-Length Biasing", U.S. Patent No. 8,949,768, February 3, 2015.
  30. P. Gupta and A. B. Kahng, "Standard Cells Having Transistors Annotated for Gate-Length Biasing", U.S. Patent No. 9,069,926, June 30, 2015.
  31. B. I. Park, A. B. Kahng, S. H. Kang and J. G. Lee, "Data-Retained Power-Gating Circuit and Devices Including the Same", U.S. Patent No. 9,166,567, October 20, 2015.
  32. P. Gupta and A. B. Kahng, "Gate-Length Biasing for Digital Circuit Optimization", U.S. Patent No. 9,202,003, December 1, 2015.
  33. A. B. Kahng and S. H. Kang, "Accuracy Configurable Adders and Methods", U.S. Patent No. 9,229,686, January 5, 2016.

Andrew B. Kahng: Published (Pending) U.S. Patent Applications

  1. O. S. Nakagawa and A. B. Kahng, "Method and System for Reshaping Metal Wires in VLSI Design", U. S. Patent Application 20070033558, February 8, 2007.