Handel Jones, CEO of International Business Strategies Inc., came to the recent Fabless Semiconductor Association Expo with a harsh warning. In a panel presentation, he said that DFM factors have slowed the ramp-up to 90-nm wafer volumes and threaten to delay 65 nm even further. And, Jones said, leakage is the major reason for DFM yield loss.

While some industry insiders see leakage as a potential culprit in yield loss, most wouldn't say it's the primary factor. Others see leakage as a design issue, not a yield problem. No one disagrees that the problem is severe at 90 nm and worse at 65 nm.

"Assuming you have defect density under control, as major companies pretty much have, leakage is the largest contributor to yield losses," Jones said. "The industry is not really 'fessing up to the problem. It was starting to be acknowledged, but I think it's being swept under the rug again at 65 nm."

Because of DFM factors, Jones said, the ramp-up to 90-nm-production wafers has taken more than two years and the ramp-up to 65 nm may take nearly three, compared with 1.5 years for 130 nm.

Whether one sees leakage as a yield problem depends somewhat on how one defines yield. Jones identified three types of yield loss — those that are process-related, reticle-related and design-related. The latter category is the one that's growing fastest, and it's primarily caused by leakage, Jones said. At 65 nm, design-related yield loss can reduce overall yields by 30 percent, he said.

The industry traditionally thinks in terms of random-defect-related yield, noted Marc Levitt, DFM platform vice president at Cadence Design Systems Inc. But if you start to consider parametric yield — basically what Jones would call design-related — then leakage and power issues become very important, he said.

"You might do a functional test and find that 70 percent of your dice are good," Levitt said. "Then you do a leakage test and find you're above a certain number of milliamps, and suddenly that 70 percent drops to 35 percent. So you could have a 35 percent yield loss because of leakage." In other words, if you have to throw a chip into the trash because it consumes too much power, it didn't yield.

Leakage can also cause hot spots in a design and perhaps even thermal runaway. In extreme cases, said Nitin Deo, vice president of marketing at DFM startup Ponte Solutions Inc., it can lead to catastrophic failures such as dislocation-

induced leakage between the source and drain of a transistor. "Leakage is one of the major sources of parametric failure," Deo said. "It is underestimated today. Designers do not have an understanding of leakage as a source of yield loss — they see it only as a performance/power factor."

Synopsys Inc. makes a distinction between random and systematic yield, with the latter referring to things that are systematically happening. "Leakage has become a key driver of that [systematic] segment of the yield-loss mechanism," said Anantha Sethuraman, vice president of DFM for the silicon engineering group.

Foundries have mixed views. Taiwan Semiconductor Manufacturing Co. Ltd. views leakage as a design rather than a yield issue, a spokesman said. But TSMC has made leakage reduction a primary goal of its recently introduced 65-nm reference flow. United Microelectronics Corp. thinks differently. "Yield loss caused by leakage is contributed by the higher power consumption, which may impact the design performance through a rise in temperature," said Suzanna Chang, senior director of marketing at UMC.

Gary Smith, chief EDA analyst at Gartner Dataquest, doesn't think leakage will cause yield loss unless it's detected through Iddq testing. But leakage can show up in power or timing failures caused by regional heating, he noted.

"Power-limited yield loss is a reality," said Andrew Kahng, founder and chairman of startup Blaze DFM Inc. "Typically, such bad parts are detected using Iddq testing." Kahng added that systematic, parametric yield loss will start to eclipse random defects at future process nodes.

An insidious problem
With the reduction in voltage thresholds and with thinner gate oxides, leakage problems are beginning to increase exponentially. Leakage may be responsible for 50 percent of a chip's power consumption at 90 nm, and perhaps as much as 80 percent at 65 nm. According to Jones' studies, both subthreshold and gate-oxide leakage are growing far faster than dynamic power, although high-k materials may slow gate-oxide leakage somewhat.

Leakage is also extremely susceptible to process, temperature and voltage variations. It is strongly interdependent with temperature, and just as leakage can cause hot spots, thermal gradients can cause huge increases in leakage. Critical-dimension variations can also wreak havoc with leakage.

Leakage variation can be as much as fivefold, said Robert Hoogenstryd, director of marketing implementation at Synopsys. "If your chip is consuming five times as much leakage current as expected, the chip will run hotter and maybe eventually melt, or not perform because of temperature inversion," he said.

Fortunately, things can be done to reduce leakage, such as swapping in high-voltage-threshold cells where performance is not critical. For this reason, many 90- and 65-nm processes provide low-Vt and high-Vt libraries. Designers can also set up voltage islands and power down sections of the chip that aren't in use.

TSMC's 65-nm reference flow offers power-gating technology based on multithreshold CMOS, letting users insert high-Vt footers to shut down circuits that are not operating. Intel Corp. claims its recently introduced its P1265 process reduces transistor leakage 1,000 times over its high-performance 65-nm process. The trade-off is that transistor performance is lower by a factor of two. IBM and Texas Instruments have also introduced 65-nm processes that claim dramatically lower leakage.

Both resolution enhancement technology and lithography simulation can also help, said Blaze DFM's Kahng. But more needs to be done. "We will see future tools that reduce leakage and improve power-limited yield while being aware of both design and process constraints," he said.