In this lab, you will learn how to simulate your design with Cadence NC-SIM
You will perform the simulation for a gate-level design. From the gate-level simulation, you will obtain VCD (value change dump) file and you can make precise power analysis with the VCD.
RTL simulation mainly verifies the functionality of hardware description language
(Verilog or VHDL). On the other hand, gate-level simulation verifies the design
timing with actual gate delays, and gate-level simulation provides functional
information for a precise power analysis.
In this lab, we will not cover the RTL simulation
and verification. We will make a Verilog simulation for a pre-implemented
8-bit adder design.
To run Lab 7, download Lab 7 tarball and extract it in your workspace.
For the gate-level simulation, you should generate SDF
(standard delay format) file first from Synopsys PrimeTime
. SDF file will provide
cell and interconnect delay information to Verilog simulator.
Then, you can run NC-SIM
-- the inputs are Verilog netlist (adder_B8.v), Verilog testbench
(adder_B8_playback_driver.v), veriog library (tcbn65gplus.v) and
the generated SDF file (adder_B8.sdf). The simulation will be run
with random input patterns during 10,000 cycles.
ieng6-205$ cp /home/linux/ieng6/ee260b/public/data/lab7.tar .
ieng6-205$ tar xvf lab7.tar
ieng6-205$ cd lab7
ieng6-205$ pt_shell -f pt_sdf.tcl
ieng6-205$ source ./NCSIM.env
ieng6-205$ ncverilog -f nc_init.cmd
After the simulation, you will have VCD
(value change dump) file
(adder_B8.vcd). With the VCD file, you can check simulation results with
. Execute Simvision with this command:
ieng6-205$ simvision &
. And, open the VCD file: [File]-[Open Database]-[Files of type: VCD Files]-[select adder_B8.vcd]-[Open]-[File Translation - OK]. In Design Browser, select [testbench] - [driver] - [uut],
then you can see internal signal names
in the window (right side).
Select input and output signals (A, B, SUM, clk), and press waveform button
You can check the simulation results as shown in this figure. You can change
the displayed value radix to decimal in the middle window (with "Cursor" text) -- [mouse right button]-[Radix]-[Decimal].
With the gate-level simulation result (VCD), you can make power analysis from
ieng6-205$ pt_shell -f pt_px.tcl
After running pt_shell, you will have a power report (pwr.rpt).
In pt_px.tcl:line 25, you can save SAIF
file from the VCD, and you can make a power analysis with SAIF
Please find manuals for NC-SIM (NC-Verilog) and PrimeTime-PX in this link
(a) Describe SDF, VCD and SAIF file formats. (b) Compare VCD and SAIF for power analysis (including pros and cons of each).
(a) In the simulation, clock cycle time is 0.3ns (see adder_B8_playback_driver.v). Please reduce the clock cycle (by 0.01ns step), and find the minimum clock cycle time which does not make errors on output values (the Verilog simulation will report the number of FAILs after comparing outputs with golden values). (b) Find the minimum clock cycle time without timing error in PrimeTime (use report_timing command in pt_shell, and check slack value and clock cycle in SDC file). (c) Explain the difference between simulation (dynamic timing analysis) and STA (static timing analysis) based on the results of (a) and (b). The result of STA will be pessimistic. Why do we use STA for design signoff?
In the power analysis, the analysis has been done with an "averaged" mode. Please make a "time-based" power analysis (see the PT-PX manual), and report dynamic, leakage and peak power results.
This webpage is maintained by: Seokhyeong Kang