ECE 260B / CSE 241A
Winter 2007
University of California, San Diego
Supported by Cadence®University Program and Synopsys®University Program

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  • ANNOUNCEMENTS

    February 23, 2007
  • ATTENTION: Prof. Kahng will hold extra office hours (3pm-5pm) next Tuesday (02/27/07).
    February 21, 2007
  • New reading assignments have been posted below.
    February 17, 2007
  • Two reference papers related to the last homework have been posted below. Scroll down to the verification (part II) section.
    February 16, 2007
  • Scroll down for the "project" page. You can find updates and notes on the project.
    February 14, 2007
  • Click here for the homework solutions (HW 5, 6 and 7).
  • Click here for the list of IP addresses of the machines in the Embedded lab.
    February 8, 2007
  • Click here for design tradeoffs of two types adder and multiplier architectures across 130nm, 90nm and 65nm technology nodes.
  • Click here for a lecture on computer arithmetic block implementation.
    February 8, 2007
  • Please check below for new reading assignments.
    January 31, 2007
  • Click here for the homework solutions (HW1 and HW2).
    January 23, 2007
  • Placement addendum slides have been posted.
    January 22, 2007
  • A reference for placement has been posted (check below).
    January 20, 2007
  • References for the Floorplanning, Partitioning and Placement lecture have been posted (check below).
    January 19, 2007
  • here is a reference for the second problem of homework 3.
    January 18, 2007
  • Click here to access WebCT.
    January 17, 2007
  • Homework 1 and Homework 2 are DUE today in the class.
    January 16, 2007
  • Equations 4.55-4.60 from the textbook and Table 4.8 have been scanned and posted here.
    January 14, 2007
  • Pages from the textbook that are related to the homework problems (1 & 2) have been scanned. Please click here to obtain them.
  • TA office hour is on Tuesday this week in EBU3B 2154 from 3pm to 4pm.
    January 12, 2007
  • Please click here to sign up for the class mail-list. Please note that all the important announcements will be broadcasted using the mail-list.
    January 9, 2007
  • Welcome to CSE241A / ECE260B class. Please make sure you check this section of the website for updates. More details will be posted soon.

  • OVERVIEW
    • ECE260B / CSE241A is a broad introduction to application-specific integrated-circuit (ASIC) implementation. It is a "guided tour" that establishes pointers into several parts of the computer engineering curriculum: circuits, VLSI, and CAD (logic synthesis, physical design, physical verification). Students come from varying backgrounds, ranging from EE/circuits to CS/algorithms. Interests may span computer architecture, IC computer-aided design, VLSI systems, and embedded systems.

  • TOPICS (I and II will be interleaved).
    • (I) Digital ASIC implementation (synthesis-place-route) flow
      • Supporting analyses: timing, noise, power
      • Cell-based place and route
      • Logic synthesis
      • Design closure issues
      • Physical verification
    • (II) Building blocks
      • Gates and interconnects
      • Clock distribution
      • Power/ground distribution
      • Embedded memory

  • LOGISTICS
    • For CSE 241A → course number: 580170 & section number: A00
    • For ECE 260B → course number: 581902 & section number: A00
    • Classroom/Time: Warren Lecture Hall (WLH) 2111, W/F 5pm - 6:20pm
    • Instructor: Prof. Andrew B. Kahng, EBU3B 2134, Tel: (858) 822-4884
      • Email: abk at cs dot ucsd dot edu
      • Office Hours: Wed 6:30-7:15pm & Thurs 4:30-5:30pm
    • Teaching Assistant: Kambiz Samadi
      • Email: ksamadi at ucsd dot edu
      • Office Hours: Mon 3-4pm with Puneet Sharma (sharma at vlsicad dot ucsd dot edu)
    • Textbook: Neil H. E. Weste and David Harris, "CMOS VLSI Design: A Circuit and Systems Perspective", Addison Wesley, 3rd Edition, 2005.
    • Prerequisite: ECE111, and ECE165 or ECE260A
    • Grading: Homework (20%) + Labs (35%) + Midterm Exam - In-Class (20%) + Final Project (25%)
    • Homeworks are due each Wednesday in class
    • Lab room: EBU3B 2154
    • Design Automation Software and Libraries:
      • Cadence SOC Encounter
      • Synopsys Design Compiler, PrimeTime and STAR-RCXT
      • TSMC 90nm/65nm libraries

  • MIDTERM

  • PROJECT

  • COURSE OUTLINE
    • Week 1 (January 10,12)
      • Wed 1/10: Introduction and ASIC Methodology. (Slides)
        • Reading Assignment:
          Review: Weste/Harris Sections 1.1-1.4
          Layout, Physical Design: Weste/Harris Sections 1.5,1.10-1.12
          Delay, Power, Scaling: Weste/Harris Sections 4.2, 4.4, 4.5, 4.9
          Visit ITRS website and explore the ITRS reports. ITRS is the international Technology Roadmap for Semiconductors which projects the semiconductors industry's future technology requirements.
      • Fri 1/12: Interconnect Scaling (C, L, R). Delay Overview. Power Overview. (Slides)
    • Week 2 (January 17,19)
      • Wed 1/17: Logic Synthesis (Guest lecturer, Dr. Cho Moon). (Slides)
      • Fri 1/19: Floorplanning, Partitioning and Placement. (Slides) , (Addendum Slides)
        Lab 1 (Synthesis and Formal Verification) assigned.
        • References for the Floorplanning, Partitioning and Placement lecture: 1, 2 and 3
        • Here is a reference on the tree covering problem.
        • Here is a reference for the second problem of the homework 3.
    • Week 3 (January 24,26)
      • Wed 1/24: Completion of Placement.
        • Click here for the reference on placement.
        • Reading assignment: Weste/Harris - Section 4.2.3 (Logical Effort)
      • Fri 1/26: Routing (Slides)
        Lab1 DUE.
        HSPICE Lab (Lab A) assigned.
        • Here is a reference on incremental optimization (ECO routing).
    • Week 4 (January 31, February 2)
      • Wed 1/31: Completion of Routing (Slides) and Power Distribution (Slides).
        • Reading Assignment:
          Weste/Harris Section 12.5 (Clock)
        Lab 2 (Physical Design) assigned.
      • Fri 2/2: Clock Distribution (Slides) and Timing (Slides).
        HSPICE Lab (Lab A) DUE.
    • Week 5 (February 7,9)
      • Wed 2/7: Completion of Clock Distribution and Timing.
        • Reading Assignment:
          For clock REQUIRED readings, click here.
      • Fri 2/9: Parasitic Estimation (Slides)
        • Cadence PKS scripts/libraries tarball needed for answering HW question #1 is posted in /rmt/dstr/hw_lab.tgz
          You can start running PKS (Physically Knowledge Synthesis) by first sourcing /rmt/tools/cadence/cadence.cshrc followed by running "pks_shell"
          You can use "pks_shell -gui" to start a GUI (only if you need it).
          You can run the script by running "source do_synthesis.tcl" in pks_shell.
        • Reading Assignment:
          Weste/Harris: Sections 9.6.1, 9.6.2 (test, scan-based test)
          LEF/DEF Reference manual (skimming is all that is needed)
          • COMPONENTS section
          • NETS section
          SOC Encounter User Guide
          • Scan chain ordering
          • Floorplanning section
          Note: The above manuals can be found at: /rmt/dstr/docs
    • Week 6 (February 14,16)
      • Mon 2/12: Lab 2 DUE.
      • Wed 2/14: Verification. (Slides)
        Lab 3 (Extraction and Timing Analysis) assigned.
      • Fri 2/16: Final Project Discussion.
        Verification (Part II) (Slides)
        • Reading Assignment:
          Please click here for readings related to the homework.
    • Week 7 (February 21,23)
    • Week 8 (February 28, March 2)
      • Wed 2/28: In-Class Exam.
      • Fri 3/2: Tapeout (Lecturer: Mr. Sorin Dobre, Staff Engineer, Qualcomm CDMA Technologies) (Slides)
    • Week 9 (March 7,9)
      • Wed 3/7: Packaging. (Slides)
      • Fri 3/9: Physical Implementation Futures.
    • Week 10 (March 14,16)
      • Wed 3/14: Final Project Presentations.
      • Fri 3/16: Final Project Presentations.
    • Finals Week (March 19 - March 23)


This webpage is maintained by: Kambiz Samadi
Last time Modified: 02/06/07
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