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EncounterTM User Guide, Product Version 3.2.1


12


Clock

This chapter describes how to use the Clock menu's clock tree synthesis (CTS) forms to build a buffer tree and balance insertion delays from the clock source to all flip-flops.

This chapter discusses the following topics:




Overview

CTS analyzes all clocks in a design (or specific clocks that you define) and inserts buffers (or inverters) to reduce or eliminate clock skew.




Flow Stage

CTS is part of the virtual prototyping stage of the EncounterTM flow. For more information about this stage, see Chapter 3, "Virtual Prototyping," in the Encounter Design Flow Guide and Tutorial.




Before You Begin

Before you run CTS on your design, make sure the following files are available:




Results

After a CTS run, CTS creates reports on the results of the run in ASCII text or HTML format. CTS also creates route guide files (for clock tree preroutes to be used during trial routing) and macro model files (for partitions or modules).




Clock - Create Clock Tree Spec

Use the Create Clock Tree Spec form to create a clock tree specification file. (The clock tree specification file uses timing constraints from the Encounter configuration file.)

For details on the contents of a clock tree specification file, see Creating a Clock Tree Specification File.

The clock tree specification file defines the clocks in the design that you want to synthesize. If a design contains several clocks, you can specify any of these clocks in the clock tree specification file, and those clocks will be synthesized during a single CTS run. You can also synthesize an individual clock tree separately and successively using its own clock tree specification file.



Related Text Commands

The following text commands provide equivalent or additional functionality:

For more information, see Chapter 2, "Clock Tree Synthesis Commands," in the Encounter Text Command Reference.



Using Clock - Create Clock Tree Spec

  1. Choose Clock - Create Clock Tree Spec.

    This opens the Create Clock Spec form.

  2. Choose from the following options:

    Buffer Footprint

    Specifies the name of the buffer's footprint from the timing library, such the .lib file or the TLF file.

    Inverter Footprint

    Specifies the name of the inverter's footprint from the timing library, such the .lib file or the TLF file.

    Save Spec To

    Specifies the name of the clock tree specification file to be created.


  3. Click OK or Apply.




Clock - Specify Clock Tree

Use the Specify Clock Tree form to select a clock tree specification file for a CTS run.



Related Text Command

The following text command provides equivalent or additional functionality:

For more information, see Chapter 2, "Clock Tree Synthesis Commands," in the Encounter Text Command Reference.



Using Clock - Specify Clock Tree

  1. Choose Clock - Specify Clock Tree.

    This opens the Specify Clock Tree form.

  2. Enter a filename in the Clock Tree File field.

  3. Click OK or Apply.



Creating a Clock Tree Specification File Template

      To create a clock tree specification file template, called template.ctstch, use the Tcl command and parameter specifyClockTree -template.

For more information on the contents of the clock tree specification file, see Creating a Clock Tree Specification File.




Clock - Clear Clock Tree Specification

Use the Clock - Clear Clock Tree Specification menu command to remove clock tree information during an Encounter session.

Note:  There is no GUI form for this command.



Related Text Command

The following text command provides equivalent or additional functionality:

For more information, see Chapter 2, "Clock Tree Synthesis Commands," in the Encounter Text Command Reference.



Clearing the Clock Tree Specification

To remove clock tree information that was loaded when you specified the clock tree specification file, complete the following step:

      Choose Clock - Clear Clock Tree Specification.



Clock - Synthesize Clock Tree

Use the Synthesize Clock Tree form to run CTS, display the clock tree results, and specify the directory and base file name for CTS reports.



Related Text Command

The following text command provides equivalent or additional functionality:

For more information, see Chapter 2, "Clock Tree Synthesis Commands," the Encounter Text Command Reference.



Using Clock - Synthesize Clock Tree

  1. Choose Clock - Synthesize Clock Tree.

    This opens the Synthesize Clock Tree form.

  2. Choose from the following options:

    Display Clock Tree

    Displays the clock tree synthesis results. Each clock instance is annotated with its phase delay value.

    Set Added Clock Buffers as Fixed

      

    Marks all the clock instances as preplaced so that any subsequent operation--such as running IPO--does not move the clock buffers.

    Handle Clock Crossover and Reconvergence

      

    Runs CTS on designs with self-reconvergent clocks and designs with crossover clocks.


    An example of self-reconvergent clocks:

    An example of two crossover clocks:

    Save Netlist

    Saves the design's netlist to a file in the Result Directory with a .v file extension.

    Save Placement

    Saves the design's placement data to a file in the Result Directory with a .place file extension.

    Save Clock Tree Synthesis Report

     

    Saves several CTS reports to files to the Result Directory. The generated reports are:

    • Detailed report file in ASCII format with a .ctsrpt file extension

    • Detailed report file in HTML format with a .rootClockPinName.html file extension

    • Summary report file in HTML format with a .ctsrpt.html file extension

    By default, a CTS trace file (with a .cts_trace file extension) is generated in the work directory to report the CTS tracing for a gated clock design.

    Save Clock Tree Routing Guide

     

    Saves the clock tree routing data to a file in the Result Directory with a .guide file extension. You can use this file as a preroute guide file when running Trial Route.

    Save Clock Tree Macro Model

     

    Saves the macro model to a file in the Result Directory with a .ctsmdl file extension. Hierarchical clock tree synthesis requires a macro model file.

    Specify the macro model file model in the clock tree specification file for a characterized block or a partitioned design.

    Save Clock Nets

    Saves the generated clock nets to a file in the Result Directory with a .ctsntf file extension. Backend detailed routers use this to guide clock net routing.

    Result Directory

    Specifies the directory name in which the CTS result files are saved.

    Base File Name

    Specifies the base name of the CTS result files. This name precedes the file extensions described in this section.


  3. Click OK.

    This saves your settings and starts CTS.




Clock - Report Clock Tree

Use the Report Clock Tree Synthesis form to control the clocks for which you want CTS to generate clock tree reports.

The clock tree reports contain information on



Related Text Command

The following text command provides equivalent or additional functionality:

For more information, see Chapter 2, "Clock Tree Synthesis Commands," in the Encounter Text Command Reference.



Using Clock - Report Clock Tree

  1. Choose Clock - Report Clock Tree.

    This opens the Report Clock Tree Synthesis form.

  2. Choose from the following options:

    Clock Selection

    Specifies the clock net(s) for which a report should be generated.

    Choose one of the following:

       

    All Clock(s)

    Selects all the clocks specified in the clock tree specification file.

       

    Selected Clock

    Selects a clock net name to be reported as specified in the field.

    Route Selection

    Selects the routing status of the clock(s) to be reported.

    Choose one of the following:

       

    Pre-Route

    Reports clock tree timing analysis results that are based on a CTS Steiner tree.

       

    Clock Route Only

    Reports clock tree timing analysis results that are based only on clock tree wires, even if other wires (such as signal net wires) exist in the design.

       

    Post-Route

    Reports post-routing clock tree timing analysis results based on clock tree wires and signal wires on the specified clock, or on all clocks in the design if no clock is specified.

    Note:  CTS halts and displays a message if the design has not been routed.

    Clock Tree Synthesis Report

       

    Specifies the filename for the report. Two reports are generated: an ASCII file and an HTML file: <top_level_module>.ctsrpt and <top_level_module>.ctsrpt.html.

    Generate Macro Model

       

    Specifies the filename for the macro model.


  3. Click OK.

    This saves your settings and generates the selected reports.




Clock - Save Clock Nets

Use the Save Clock Nets form to save a clock net file that you can use for running detailed routing of the clock tree.



Related Text Command

The following text command provides equivalent or additional functionality:

For more information, see Chapter 2, "Clock Tree Synthesis Commands," in the Encounter Text Command Reference.



Using Clock - Save Clock Nets

  1. Choose Clock - Save Clock Nets.

    This opens the Save Clock Nets form.

  2. Choose from the following options:

    Clock Selection

    Specifies which clock nets to save.

    Choose one of the following:

       

    All Clock(s)

    Saves all clocks in the clock tree specification file.


    Selected Clock

    Saves a specific clock net.

    Clock Tree Synthesis Save Clk Nets

       

    Specifies the filename for the report. The default report name is <top_level_module>.ctsntf.


  3. Click OK.




Clock - Clock Tree Browser

Use the Clock Tree Browser to view and identify the synthesized clock tree, the added clock buffers, and the added delay elements. In addition, you can control the display of the resulting clock tree, phase delay, and minimum and maximum paths in the Physical view.

To view the CTS results, you must be in the Physical view.

In the Physical view, the clock tree instances are color coded to represent their clock phase delay value. Colors at the red end of the spectrum indicate the greatest phase delay; colors at the blue end of the spectrum indicate the smallest phase delay.

For more information on the Clock Tree Browser, see Using Clock - Clock Tree Browser.

You can change the color coding preference using the Color Preference form (see "Modifying Colors").

The naming conventions for the added clock buffer instances and clock net names are as follows:

The underscore (_) in the above naming conventions represents any name delimiter you specify with the NameDelimiter statement in the clock tree specification file.

Note:  Two underscores follow rootClockName, unless you specify the UseSingleDelim statement in the clock tree specification file.

For more information on naming conventions, see NanoRoute Attribute Section.



Using Clock - Clock Tree Browser

  1. Choose Clock - Clock Tree Browser.

    This opens the Clock Tree Browser window.

  2. Highlight an item in the Specified Clock List, then click Select.

  3. Choose from the following options:

    Route Selection

    Selects the routing status of the clock(s) to be displayed.

    Choose one of the following:

       

    Pre-Route

    Displays clock tree timing analysis results that are based on a CTS Steiner tree.

       

    Clock Route Only

    Displays clock tree timing analysis results that are based only on clock tree wires, even if other wires (such as signal net wires) exist in the design.

       

    Post-Route

    Displays post-routing clock tree timing analysis results based on clock tree wires and signal wires on the specified clock, or on all clocks in the design if no clock is specified.

    Note:  CTS halts and displays a message if the design has not been routed.


  4. Click OK.

    CTS builds the hierarchical clock tree and replaces the original browser display with a diagram of the clock tree:

    Components in the clock tree appear in the following colors:

    • Blue for leaf pins

    • Green for buffers, inverters, or gates

  5. To save the contents of the Clock Tree Browser to a file, choose Browser - Save.

    This opens the Save Clock Tree Browser form.

  6. Type the name of the file to which you want to save the Clock Tree Browser data, then click OK.

  7. To close the Clock Tree Browser at any time without saving its contents to a file, choose Browser - Close.



Editing Instances

You can edit instances from the Clock Tree Browser by using the following browser menu commands. The following table summarizes the choices available for editing instances:

Edit - Resize

Displays the Select Cell form. Use this form to select a cell to use when resizing an instance in the Clock Tree Browser.

Edit - Insert at input

Inserts buffers, inverters, or clocked leaf instances as close as physically possible to the chosen input.

  1. Click on the instance at whose input you want to insert a buffer or inverter.

  2. Select Edit - Insert at input.

    The Insert Specified Cell form appears, showing a list of cells from the clock tree specification file.

  3. In the Insert Specified Cell form, select the cell you want to insert.

  4. Click OK.

The inserted cell appears at the input of the instance you selected.

Edit - Insert at output

Inserts buffers or inverters as close as physically possible to the chosen output.

  1. Click on the instance at whose input you want to insert a buffer or inverter.

  2. Select Edit - Insert at output.

    The Insert Specified Cell form appears, showing a list of cells from the clock tree specification file.

  3. In the Insert Specified Cell form, select the cell you want to insert.

  4. Click OK.

The inserted cell appears at the output of the instance you selected.

Note:  You cannot insert buffers or inverters at the output of flip-flops.

Edit - Delete

Deletes buffers or inverters.

      Click on a buffer or inverter, then select Edit - Delete.

Edit - Reconnect

Reconnects clocked leaf instances that have been revised within the browser. The placement of such instances remains the same, but CTS changes the connections between the instances.

Note:  You can only reconnect leaf cells. CTS does not refine placement after reconnecting leaf cells.

Edit - Highlight

Highlights selected buffers, inverters, or clocked leaf instances in the Physical view.

Edit - Zoom highlighted

Zooms into selected buffers, inverters, or clocked leaf instances in the Physical view.

Edit - DeHighlight

Dehighlights selected buffers, inverters, or clocked leaf instances in the Physical view.

Display - Physical view

Provides three choices

Note:  The name of this menu choice was changed from Placement view.


Use the Clock Tree Browser Insert and Delete commands only on clock tree nets that you have not yet routed. If you use the Clock Tree Browser on routed nets, CTS will create unconnected wires in the design.


Resizing Instances

To change instance sizes, complete the following steps:

  1. Use the left mouse button to highlight an instance in the Clock Tree Browser.

  2. Choose Edit - Resize.

    This opens the Select Cell form.

    These cells have the same footprint as the highlighted instances. Footprints are defined in the timing library.

  3. Select a cell in the list.

  4. Click OK.

    The selected instance is replaced with the selected cell size.



Expanding and Collapsing Branches

You can expand or collapse branches in the Clock Tree Browser by clicking the symbols next to the instance names.

Alternatively, you can use the following menu commands:

Display - Expand all

Shows all branches in the clock tree.

Display - Expand to instance ...

   

Opens all branches of the clock tree leading to a specific instance. This displays the path from the root to the specified instance. Choosing this option opens the query form in which you can do the following:

  1. Enter an instance name in the Instance name to expand to field.

  2. Click OK.

The browser displays the path (in red) from the clock root pin to the specified instance.

Display - Expand from instance

   

Opens all branches beginning with the highlighted instance.

Display - Collapse from instance

  

Closes all branches beginning with the highlighted instance.

Display - Refresh

Updates the colors in the browser.




Displaying the Clock Tree Histogram

You can display a histogram that reports the distribution of minimum trigger edge delay and maximum trigger edge delay (in picoseconds) for each terminal in a clock.

The vertical axis of the histogram shows the number of sinks that have the delay shown (in picoseconds) on the horizontal axis of the histogram.

The gradation of the picosecond increments in the histogram depends on the range of delay values. The example below shows one-picosecond delay increments; if the range of delay values were greater, the increments would be greater, too.

To display the histogram, complete the following step:

      In the Clock Tree Browser, select Display - Trigger Edge Delay.


Adding and Removing Columns

The Clock Tree Browser contains columns that list various types of information. You can add or remove the columns that are displayed by using the following browser menu commands:

Display - Hide/Show - Instance name

   

Adds or removes the instance_name column that displays the instance names associated with each branch in the clock tree.

Display - Hide/Show - Trig edge

   

Adds or removes the trig_edge column that displays the triggering edge type for instances in the clock tree.

Hides or shows the Trig edge column in the viewer. Trig edge refers to downstream trigger edges.


Display - Hide/Show - Trig edge skew

   

Adds or removes the trig_edge_skew column that displays the triggering edge skew values for instances in the clock tree.

Hides or shows the Trig edge skew column in the viewer. Trig edge skew refers to downstream trigger edges.


Display - Hide/Show - Rise delay

   

Adds or removes the rise_delay column that reports the downstream rise delays.

Display - Hide/Show - Fall delay

   

Adds or removes the fall_delay column that reports the downstream fall delays.

Display - Hide/Show - Rise skew

   

Adds or removes the rise_skew column that reports the downstream skew.

Display - Hide/Show - Fall skew

   

Adds or removes the fall_skew column that reports the downstream skew.

Display - Hide/Show - Input delay

   

Adds or removes the input_delay column that reports the downstream input delays.

Display - Hide/Show - Input tran

   

Adds or removes the input_tran column that reports the downstream input transition values.




Displaying Path and Phase Delay Information

You can use the Clock Tree Browser to display minimum and maximum paths, as well as phase delays, in the design display area while viewing your design in Physical view.

To display the phase delays of clock instances, complete the following step:

      Choose Display - Physical View - Phase delay.

Colors at the red end of the spectrum indicate the greatest phase delay; colors at the blue end of the spectrum indicate the smallest phase delay.

To display the clock paths with the minimum and maximum delays, complete the following step:

      Choose Display - Physical View - Min/Max paths.

The clock path with minimum delay is blue; the clock path with maximum delay is red.

To clear the clock tree display in the design area, complete the following step:

      Choose Display - Physical View - Clear display.


Displaying Instance Information

To display information in the Encounter console about a selected instance, complete the following steps:

  1. Highlight an instance in the Clock Tree Browser using the left mouse button.

  2. Choose Report - Instance info.

    The following information is written to the Encounter console:

    • Instance name

    • Cell

    • Level

    • Input delay

    • Input transition

    • Downstream triggering edge type

    • Downstream triggering edge skew

    • Downstream rise delay

    • Downstream fall delay

    • Downstream rise skew

    • Downstream fall skew



Related Text Command

The following text command provides equivalent or additional functionality:

For more information, see Chapter 2, "Clock Tree Synthesis Commands," in the Encounter Text Command Reference.




Clock - Display - Display Clock Tree

Use the Display Clock Tree form after running CTS to display the clock tree for all clocks or for a single clock.



Related Text Command

The following text command provides equivalent or additional functionality:

For more information, see Chapter 2, "Clock Tree Synthesis Commands," in the Encounter Text Command Reference.



Using Clock - Display - Display Clock Tree

  1. Choose Clock - Display - Display Clock Tree.

    This opens the Display Clock Tree form.

  2. Choose from the following options:

    Clock Selection

    Determines the clock(s) to be displayed.

    Choose one of the following:

       

    All Clock(s)

    Displays all clocks in the clock tree specification file.

       

    Selected Clock

    Displays a specific clock net.

    Route Selection

    Selects the routing status of the clock(s) to be displayed.

    Choose one of the following:

       

    Pre-Route

    Displays clock tree timing analysis results that are based on a CTS Steiner tree.

       

    Clock Route Only

    Displays clock tree timing analysis results that are based only on clock tree wires, even if other wires (such as signal net wires) exist in the design.

       

    Post-Route

    Displays post-routing clock tree timing analysis results based on clock tree wires and signal wires on the specified clock, or on all clocks in the design if no clock is specified.

    Note:  CTS halts and displays a message if the design has not been routed.

    Display Section

    Determines the kind of information to display in the Physical view.

    Choose one of the following:

       

    Display Clock Tree

    Displays clock tree and instances.

    Choose one of the following:

       

       

    All Level: Displays all levels of the clock tree.

       

       

    Bottom Level (non-gated clock tree only): Displays the bottom level of non-gated clock trees.

       

       

    Selected Level (non-gated clock tree only): Displays the non-gated clock tree level specified by the user.

       

    Display Clock Phase Delay

    Displays only the selected clock tree instances' phase delay.

       

    Display Clock Min/Max Path

    Displays fly lines for the minimum (blue) and maximum (red) clock path delays.


  3. Click OK.

The displayed instances' phase delays are color coded. Colors at the red end of the spectrum indicate the greatest phase delay. Colors at the blue end of the spectrum indicate the smallest phase delay. In addition, each clock instance is annotated with its phase delay value.

You can view and change the color coding preference by using the Color Preference form (see "Modifying Colors").




Clock - Display - Clear Clock Tree Display

Use the Clock - Display - Clear Clock Tree Display menu command to clear the clock tree display.

Note:  There is no GUI form for this command.



Related Text Command

The following text command provides equivalent or additional functionality:

For more information, see Chapter 2,"Clock Tree Synthesis Commands," in the Encounter Text Command Reference.



Clearing the Clock Tree Display

To clear the clock tree display in the design area, complete the following step:

      Choose Clock - Display - Clear Clock Tree Display.



Design Strategies

The following sections provide general CTS design guidelines or usage tips.



CTS Operation Modes

There are two modes for running CTS: manual and automatic.

Manual CTS Mode

You can run manual CTS on a clock net and specify the levels of clock buffers. CTS builds the clock buffer tree according to the clock tree specification file, generates the clock tree topology, and balances the clock phase delay with inserted clock buffers.

The following is an example of clock tree specification file syntax and a graphic representation of that syntax:

Automatic CTS Mode

You can run automatic CTS to synthesize the clock design on a clock net or on a gated clock design.

Automatic CTS on Nets

For automatic CTS on a net, CTS builds the clock buffer tree according to the clock tree specification file, generates the clock tree topology, and balances the clock phase delay with appropriately sized, inserted clock buffers.

The following is an example of clock tree specification file syntax for automatic CTS on a net and a graphic representation of the syntax:

Automatic CTS for Gated Clocks

For automatic gated CTS, CTS traces the clock tree starting from a root pin. The tracing begins at the root pin, then continues through the buffers, inverters, multi-output cells, and gated instances to establish the clock tree. The tracing stops at

After the tracing, CTS builds the clock buffer tree topology to balance the clock phase delay with inserted clock buffers.

Note:  Cadence recommends using the ckSynthesis -check command to check the gated clock tree of your design before running automatic gated CTS mode. After running the command, review the trace report file, topModule.cts.trace. If tracing fails, the -forceReconvergent parameter of the ckSynthesis command could resolve tracing failures.

The following is an example of clock tree specification file syntax for automatic CTS on a gated clock and a graphic representation of the syntax:



Macro Model Delay

You use the MacroModel statement to specify pin delays. A macro model is a block with synthesized clock trees, and thus has delays that have been identified.

There are three ways to define the macro model:

Delay units for MacroModel statements must be specified in nanoseconds (ns) or picoseconds (ps), for example, 200ps, 1ns.

Capacitance units for MacroModel statements must be specified in picofarads (pF) or femtofarads (fF), for example, 0.2pf, 130ff.

For illustrations of MacroModel behavior, see Automatic CTS on Nets and Automatic CTS for Gated Clocks.



Clock Grouping

Clock grouping is available in automatic CTS mode. All clock root pin names entered into a clock group that will have their sinks meet the maximum skew as specified in the clock tree specification file. CTS balances the clock tree roots as if they were one tree.

The sinks of all clock root pins listed in a ClkGroup statement will meet the maximum skew value set in the clock tree specification file. Clock grouping inserts delays to balance the clocks, and attempts to meet clock skew for all clocks.

Note:  You can define more than one clock group in the clock tree specification file.

The following is an example of clock group syntax and its graphical representation:

Note:  All ClkGroup statements must be specified in lines following macro model line(s), and before any clock specification.



Hierarchical Clock Tree Analysis

Encounter designs clock trees in a two-step, bottom-up fashion.

Within Encounter, the designing of the clock tree is done bottom-up in two steps. After partitioning the design, you can run CTS on each partition individually. Once the partitions are synthesized, the top-level partition runs CTS hierarchically. So CTS runs at the top-level partition, and the partitions' clock tree results are treated as macro model instances.

To generate the partition macro models, use the Synthesize Clock Tree form (Clock - Synthesize Clock Tree) or the following command when running CTS for the partition:

ckSynthesis -macromodel fileName

The rise time, fall time, and input capacitance for the clock pins are characterized, and the fileName output model file is used when creating the top-level partition's clock tree specification file. Running CTS for the top-level partition balances the clock phase delay between the top-level and the partitions.

The macro model specifications for each partition are at the top of the clock tree specification file.

For example, in a design with three partitions (blockA, blockB and blockC), you should first synthesize the partitions individually. To run CTS on the partition's blocks, you should add the AddDriverCell statement in the clock tree specification file. Use the AddDriverCell driver_cell_name statement for block-level CTS to place a driver cell name at the closest possible location to the clock port location. For example:

AutoCTSRootPin blockA/clk
....
...
AddDriverCell CLKBUF8
End

CTS adds buffer CLKBUF8 after the input pin, as shown in the following figure:

After running CTS on the blocks, run CTS on the top level of the design. To run top-level CTS, you must include all the macro models from block-level CTS in the clock tree specification file.

If your top-level design has a large amount of blockage and is limited in routing resources, you should add the Obstruction Yes statement in the clock tree specification file. That statement instructs CTS to run the detail maze router to detect the obstruction (which increases CTS runtime). Cadence recommends using this statement only when routing resources are extremely limited, such as in top-level CTS.

The following is an example of the Obstruction Yes command in the clock specification file:

MacroModel port blockA/clk 900ps 800ps 900ps 800ps 17ff
MacroModel port blockB/clk 1100ps 1000ps 1100ps 1000ps 18ff
MacroModel port blockC/clk 500ps 400ps 500ps 400ps 19ff
AutoCTSRootPin clk
....
...
Obstruction Yes
End


Module Placement Utilization

Make sure the modules' placement utilization (which contains the clock nets) is set to 5%-7% less than the desired final chip utilization (placement density). This provides placement resources for adding clock buffers during CTS.



Clock Designs with Tight Area

For a clock design that is limited to a tight area, use the Specify Cell Padding form
(Place - Specify - Cell Padding) to create placement resources near clocked flip-flop cell types.



Pin Balancing for Blocks or Standard Cell Instances

CTS can balance a pin of a block or standard cell instance. These instance models are user specified. All the clock phase delays and skews of the synthesized to clocks are balanced with the macro or standard cell instance. The macro instance pin delay values are modeled in the clock tree specification file.



Timing Model Requirement for Cells

Make sure all cells have a timing model. If a cell does not have a timing model, CTS will not trace through the gate, and may set the gate's input pin as a leaf pin.




Creating a Clock Tree Specification File

Before you can run CTS, you must create a clock tree specification file by:

This file contains the following information on the clock or clocks you want to analyze with CTS:

You can create a clock tree specification file for all the clocks in your design, for a subset of clocks in your design, or for a single clock.

The general sections of the clock tree specification files must appear in the order given above. However, the individual statements within each section can appear in any order.

Example of a Clock Tree Specification File

The following example illustrates the content of a clock tree specification file:

TimingConstraintFile dtmf_cts.tc
UseSingleDelim YES
NameDelimiter |
MacroModel pin freg/mod004048/CLK 20ps 18ps 20ps 18ps 30ff
ClkGroup
+ CGEN_1
+ CGEN_2
RouteTypeName CK1
NonDefaultRule rule1
PreferredExtraSpace 1
TopPreferredLayer 5
BottomPreferredLayer 4
Shielding VDD VSS
End
#Example of manual CTS specification information
ClockNetName CK
LevelNumber 2
LevelSpec 1 1 BUFX2
LevelSpec 2 2 BUFX2
PostOpt NO
End
AutoCTSRootPin cgen/i_5/Y
MaxDelay 5.0ns
MinDelay 0ns
MaxSkew 250ps
SinkMaxTran 550ps
BufMaxTran 550ps
NoGating NO
DetailReport YES
Obstruction YES
RouteType CK1
RouteClkNet YES # Turns on NanoRoute. The default value is NO
PostOpt NO # Turns off optimization. The default value is YES
Buffer BUFX2 BUFX4 BUFX8 BUFX12 INVX1 
MaxCap 
+ BUFX2 1pf
+ BUFX4 1pf
+ BUFX8 1pf
+ BUFX12 1pf
ThroughPin
+ df/mod000446/CK
LeafPin
+ PCLK66_gate_i/A rising
LeafPort
+ ssfd2s/D rising
PreservePin
+ cgen/mod000043/A rising
ExcludedPin
+ freg/mod004048/CLK 
ExcludedPort
+ DFF_B/CLK 
End

Timing Constraint File Specification

You can optionally define a timing constraint file for use during CTS.

      To specify a timing constraint file, the TimingConstraintFile fileName statement must be the first statement in the clock tree specification file.

Naming Attributes Section

The following table describes the entries for the naming attributes section:

NameDelimiter delimiter

   

Allows you to customize the name delimiter that CTS uses when inserting buffers and updating clock root and net names. There are no restrictions on the characters you can use for name delimiters. For example:

NameDelimiter # creates names with the format clk##L3#I2, rather than the default format, clk__L3_I2.

Insert the NameDelimiter statement after MacroModel and ClkGroup statements but before an AutoCTSRootPin statement.

Note:  If you have multiple NameDelimiter statements in the clock tree specification file, CTS uses only the last NameDelimiter statement in the file.

Note:  The NameDelimiter and UseSingleDelim statements are independent of each other.

UseSingleDelim YES | NO

   

Instructs CTS whether to use single name delimiters after the first element in clock root and net names. For example:

UseSingleDelim YES creates clock and net names with the format clk_L3_I2, rather than the default format, clk__L3_I2.

By default, CTS always inserts double (or, in some cases, multiple) name delimiters after the first element of clock root or net names. The UseSingleDelim YES statement overrides this behavior by instructing CTS to use only a single delimiter after the first element of the name:

Insert the UseSingleDelim statement after MacroModel and ClkGroup statements but before an AutoCTSRootPin statement.

Note:  The UseSingleDelim and NameDelimiter statements are independent of each other.


NanoRoute Attribute Section

The following table describes the entries for the section of the clock tree specification file that deals with attributes that CTS passes to NanoRoute Ultra).

RouteTypeName name

Specifies the routing type for which you are defining routing attributes.

NonDefaultRule ruleName

   

Specifies the LEF NONDEFAULTRULE statement that the router should use.

Default: If you do not use this statement, the router uses the default routing rule.

PreferredExtraSpace [0-3]

   

Specifies the spacing attribute, with which to add space around clock wires.

Default: If you do not use this statement, CTS uses a preferred extra space value of 1.

TopPreferredLayer number

   

Specifies the top-most preferred routing layer.

Default: If you do not use this statement, CTS uses layer 3 as the top-most preferred routing layer.

BottomPreferredLayer number

   

Specifies the bottom-most preferred routing layer.

Default: If you do not use this statement, CTS uses layer 2 as the bottom-most preferred routing layer.

Shielding PGNetName ...

   

Defines the power and ground net names.

End

Marks the end of the NanoRoute Ultraattribute section.


Macro Model Data Section

The following table describes the entries for the macro model port data section:

MacroModel port cellName_or_portName delay_and_capacitance_values

   

Specifies the name of the macro model cell or port.

maxRiseDelay{ns|ps}

Specifies the maximum rise delay in nanoseconds or picoseconds.

minRiseDelay{ns|ps}

Specifies the minimum rise delay in nanoseconds or picoseconds.

maxFallDelay{ns|ps}

Specifies the maximum fall delay in nanoseconds or picoseconds.

minFallDelay{ns|ps}

Specifies the minimum fall delay in nanoseconds or picoseconds.

inputCap{pf|ff}

Specifies the input capacitance in picofarads or femtofarads.


The following table describes the entries for the macro model pin data section:

MacroModel pin pinName delay_and_capacitance_values

   

Specifies the name of the macro model pin.

maxRiseDelay{ns|ps}

Specifies the maximum rise delay in nanoseconds or picoseconds.

minRiseDelay{ns|ps}

Specifies the minimum rise delay in nanoseconds or picoseconds.

maxFallDelay{ns|ps}

Specifies the maximum fall delay in nanoseconds or picoseconds.

minFallDelay{ns|ps}

Specifies the minimum fall delay in nanoseconds or picoseconds.

inputCap{pf|ff}

Specifies the input capacitance in picofarads or femtofarads.


Clock Grouping Data Section

The following table describes the entries for the clock grouping data section:

ClkGroup
+ clockRootPinName
+ clockRootPinName
...

Specifies two or more clock domains for which you want CTS to balance the skew.


Clock Tree Topology Section

The clock tree topology section provides a method for you to manually define buffers at particular levels. The following table describes the entries for the clock tree topology section:

ClockNetName netName


   

Specifies the name of the clock net.

LevelNumber number

Specifies the clock level number.

LevelSpec levelNumber numberOfBuffers bufferType

   

Provides the specifications for an individual clock level.

Specify all the following information:

   

levelNumber

Sets the level number in the clock tree.

   

numberOfBuffers



Specifies the total number of buffers CTS should allow on the specified level of the clock tree.

   

bufferType

Specifies the buffer type (based upon the LEF file).

End

Marks the end of a clock tree topology section.


Automatic Gated CTS Section

The following table describes the entries for the automatic gated CTS section:

AutoCTSRootPin clockRootPinName


   

Specifies the name of the clock root pin name from which to start tracing.

MaxDelay number{ns|ps}

Specifies the maximum phase delay constraint.

Default: If you do not use this statement, CTS uses a maximum phase delay constraint of 10 ns.

MinDelay number{ns|ps}

Specifies the minimum phase delay constraint.

Default: If you do not use this statement, CTS uses a minimum phase delay constraint of 0.0 ns.

SinkMaxTran number{ns|ps}

Specifies the maximum input transition time constraint for sinks (clock pins).

Default: If you do not use this statement, CTS uses a maximum sink transition time constraint of 400 ps.

BufMaxTran number{ns|ps}

Specifies the maximum input transition time constraint for buffers.

Default: If you do not use this statement, CTS uses a maximum buffer transition time constraint of 400 ps.

MaxSkew number{ns|ps}

Specifies the maximum skew between sinks (clock pins).

Default: If you do not use this statement, CTS uses a maximum skew constraint of 300 ps.

NoGating { rising | falling | NO }

   

Sets the criteria for tracing through logic gates.

Choose only one of the following:

   

rising

Stops tracing through a gate (including buffers and inverters) and treats the gate as a rising-edge-triggered flip-flop clock pin.

   

falling

Stops tracing through a gate (including buffers and inverters) and treats the gate as a falling-edge-triggered flip-flop clock pin.

   

NO

Allows CTS to trace through clock gating logic.

Default: This is the default behavior for gated-clock designs. (If you omit the NoGating statement, CTS traces through clock gating logic.

AddDriverCell driver_cell_name

   

Places a driver cell name at the closest possible location to the clock port location for block-level CTS.

MaxDepth number

Sets the maximum depth of clock tree tracing.

Default: If you do not use this statement, CTS limits the number of levels of clock tree tracing to 1024.

RouteType routeTypeName

Specifies the name of the clock for which you are defining routing attributes.

DetailReport YES | NO

Determines whether CTS provides a detailed report. The detailed report includes timing information for every component in the design. The non-detailed report contains only summary information for the design.

Default: If you do not use this statement, CTS does not provide a detailed report.

RouteClkNet YES | NO

Specifies whether CTS routes clock nets.

Default: If you do not use this statement, CTS does not route clock nets. In other words, the default behavior is as if you had specified RouteClkNet NO.

PostOpt YES | NO

Specifies whether CTS resizes buffers or inverters, refines placement, and corrects routing for signal and clock wires.

Default: If you do not use this statement, CTS performs resizing, refined placement, and routing correction. In other words, the default behavior is as if you had specified PostOpt YES.

Buffer cell1 cell2 cell3 ...

   

Specifies the names of buffer cells to use during automatic, gated CTS.

LeafPin
+
pinName rising | falling
+ ...

   

Marks the pin as a "leaf" pin for non-clock-type instances, stops tracing, and balances clock skew.

Choose one of the following:

   

rising

CTS treats the pin as a rising-edge-triggered flip-flop clock pin.

   

falling

CTS treats the pin as a falling-edge-triggered flip-flop clock pin.

LeafPort
+
portName rising | falling
+ ...

   

Marks the port as a "leaf" port for non-clock-type instances, stops tracing, and balances clock skew.

Choose one of the following:

   

rising

CTS treats the pin as a rising-edge-triggered flip-flop clock pin.

   

falling

CTS treats the pin as a falling-edge-triggered flip-flop clock pin.

ExcludedPin
+
pinName
+ ...

Treats the pin as a non-leaf pin, and prevents tracing and skew analysis of the pin.

ExcludedPort
+
portName
+ ...

Treats the port as a non-leaf port, and prevents tracing and skew analysis of the pin.

ThroughPin
+
pinName
+ ...

Traces through the pin, even if the pin is a clock pin.

PreservePin
+
inputPinName
+ ...

Preserves the netlist for the pin and pins below the pin in the clock tree. However, CTS considers any synchronized pins after the pin when computing skew.

DefaultMaxCap capvalue{pf|ff}

   

Instructs CTS to use the specified maximum capacitance value instead of the maximum capacitance values in other files.

CTS adheres to the following priority when using maximum capacitance values:

  1. MaxCap statements in the clock tree specification file.

  2. DefaultMaxCap statements in the clock tree specification file.

  3. Maximum capacitance values in the SDC file.

  4. Maximum capacitance values in the .lib file.

Note:  The DefaultMaxCap statement must appear before the MaxCap statement.

MaxCap
+
bufferName1 capValue1{pf|ff}
+
bufferName2 capValue2{pf|ff}
+ ...

   

Specifies that a buffer should be inserted if the given capacitance value is exceeded.

Default: If you do not specify maximum capacitance values in the clock tree specification file, CTS uses the maximum capacitance values in the timing library.

   

bufferName

Specifies the name of the buffer for which you specify a maximum capacitance value.

   

capValue

Specifies the maximum capacitance for the buffer, in picofarads (pF).

End

Marks the end of an automated gated CTS section.


Log File Headings

Given particular settings for the RouteClkNet and PostOpt statements, and for the reportClockTree command, the encounter.log file reports results in the following sections of the log file:

Clock tree specification file statements

Example clock tree text command sequences

Encounter log file section heading: Clock clockName plus--

RouteClkNet NO

ckSynthesis
globalDetailRoute
reportClkTree -clk clock

Pre-Route Timing Analysis

RouteClkNet YES

ckSynthesis
globalDetailRoute
reportClkTree -clk clock -clkRouteOnly

Clk-Route-Only Timing Analysis

RouteClkNet YES
PostOpt YES

ckSynthesis
globalDetailRoute
reportClkTree -clk clock -postRoute

Post-Route Timing Analysis



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