The ISPD98 Circuit Benchmark Suite

Warning! The hMetis results in the paper are buggy.
Please use the correct new data.

From 1985-1993, the MCNC regularly introduced and maintained benchmark suites for use by the Design Automation community. These benchmarks are currently being maintained by The Collaborative Benchmarking Laboratory. However, no circuits for partitioning and placement problems have been introduced over the last five years. Consequently, the second largest circuit in the existing public set of benchmarks has just over 25,000 cells whch is considered small by today's standards. This Web site introduces the ISPD98 circuit benchmark suite which contains 18 circuits ranging from 13,000 to 210,000 cells. See the ISPD paper for more details, along with several sets of experimental results on these circuits. More recent results for the ISPD-98 benchmarks can be found in the Partitioning Slot of the MARCO/GSRC bookshelf for VLSI CAD algorithms.
Any contributions or suggestions should be sent to Chuck Alpert.

Benchmark Characteristics
Benchmark File Format
Download the Circuits
Also see performance comparisons of hMetis vs UCLA MLPart : 2% and 10% tables.

Benchmark Characteristics

Benchmark File Format

Each benchmark comes with 3 files, a .net file, a .are file and a .netD file. The first two formats have been around for a decade, while the third format is a new one is like .net format, but it also contains signal direction. If you are starting a new tool from scratch, use .netD and .are format, but if you want backwards compatibility with other tools, .net format should be used.

Perl script that translates these formats into the hMetis partitioner format.

Net Format

Each netlist header has five entries which are
pad offset

The list of nets follows. Each net is simply a subset of modules which are either cells or pads. Cells are numbered from 0 to pad offset (inclusive). Pads are numbered from 1 to (#Modules - pad offset - 1). (Please do not blame me for the unintuitive numbering scheme). Cells are prefaced by an "a", pads by a "p". The beginning of each net is denoted by an "s".

For the above example with 4 cells, 3 pads, 5 nets and 13 pins, the net file is given by
p1 s 1
a0 l
a1 l
a0 s 1
a2 l
a3 l
a1 s 1
a2 l
a3 l
a2 s 1
p2 l
a3 s 1
p3 l

The .are file is a list of the size of each module. It is simply a list of cells and pads, each followed by its area. In the example, the .are file is given by
a0 1
a1 3
a2 4
a3 2
p1 0
p2 0
p3 0

Finally, .netD is just like .net except that each module in a net is labeled as either an input (I), output (O) or bidirectional (B) pin for that net. In other words, If a module is labeled with an I, it is a sink for the net; if it is labeled with an O, it is a source for the net. This can enable one to deduce signal directions over the circuit. The .netD file for the example is given by
p1 s O
a0 l I
a1 l I
a0 s O
a2 l I
a3 l I
a1 s O
a2 l I
a3 l I
a2 s O
p2 l I
a3 s O
p3 l I

Download the Circuits ibm01.are ibm01.netD ibm01.tar.gz (all 3 files) ibm02.are ibm02.netD ibm02.tar.gz (all 3 files) ibm03.are ibm03.netD ibm03.tar.gz (all 3 files) ibm04.are ibm04.netD ibm04.tar.gz (all 3 files) ibm05.are ibm05.netD ibm05.tar.gz (all 3 files) ibm06.are ibm06.netD ibm06.tar.gz (all 3 files) ibm07.are ibm07.netD ibm07.tar.gz (all 3 files) ibm08.are ibm08.netD ibm08.tar.gz (all 3 files) ibm09.are ibm09.netD ibm09.tar.gz (all 3 files) ibm10.are ibm10.netD ibm10.tar.gz (all 3 files) ibm11.are ibm11.netD ibm11.tar.gz (all 3 files) ibm12.are ibm12.netD ibm12.tar.gz (all 3 files) ibm13.are ibm13.netD ibm13.tar.gz (all 3 files) ibm14.are ibm14.netD ibm14.tar.gz (all 3 files) ibm15.are ibm15.netD ibm15.tar.gz (all 3 files) ibm16.are ibm16.netD ibm16.tar.gz (all 3 files) ibm17.are ibm17.netD ibm17.tar.gz (all 3 files) ibm18.are ibm18.netD ibm18.tar.gz (all 3 files)

Chuck Alpert's Home Page | MCNC Benchmarks in net format | Partitioning Codes | Publications | UCLA VLSI CAD Laboratory