The sizing problem in VLSI design seeks to tune the circuit
parameters (i.e., gate width, gate length and threshold voltage)
to optimize a tradeoff of speed, area and power of circuit.
Many gate-sizing heuristics have been proposed over the past
two decades, but research has suffered from the lack of any
systematic way of assessing the quality of the proposed
This benchmark suite includes (i) benchmark testcases
(libraries, netlists and timing constraints), (ii) leakage power
optimizers from UCSD/UCLA and (iii) results for the
benchmark testcases. With the provided testcases and evaluation
results, systematic and quantitative comparisons will be possible
for other existing or newly proposed gate-sizing algorithms.