UC Benchmark Suite for Gate Sizing








Last Modified: September 6, 2011
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Andrew B. Kahng, Seokhyeong Kang, Jingwei Lu (UCSD)

Puneet Gupta, John Lee, Santiago Mok, XinHeng Huang (UCLA)

Motivation

The sizing problem in VLSI design seeks to tune the circuit parameters (i.e., gate width, gate length and threshold voltage) to optimize a tradeoff of speed, area and power of circuit. Many gate-sizing heuristics have been proposed over the past two decades, but research has suffered from the lack of any systematic way of assessing the quality of the proposed algorithms.

This benchmark suite includes (i) benchmark testcases (libraries, netlists and timing constraints), (ii) leakage power optimizers from UCSD/UCLA and (iii) results for the benchmark testcases. With the provided testcases and evaluation results, systematic and quantitative comparisons will be possible for other existing or newly proposed gate-sizing algorithms.

Overview

Acknowledgments

This benchmark suite is supported by the National Science Foundation (NSF).

  • NSF CCF-{0811866, 0811832}: "Research on Benchmarking and Robustness of VLSI Sizing Optimizations" PIs: Andrew B. Kahng (UCSD) and Puneet Gupta (UCLA)

UCLA research for gate sizing can be found in this link: Robustness and Benchmarking of Gate Sizing

We appreciate any feedback you may have on the testcases, results or web site.