UCSD VLSI CAD LABORATORY














Last Modified: October 11, 2006

Topics:

  1. The VLSI Design-Manufacturing Interface
  2. VLSI Interconnect Performance Analysis and Optimization
  3. VLSI Interconnect Synthesis and Prediction
  4. Technology Extrapolation and the "Living Roadmap"
  5. MARCO GSRC Calibrating Achievable Design (C.A.D.) Theme
    1. The GTX system
    2. The GSRC Bookshelf for Fundamental CAD Algorithms
    3. A Metrics System for Design Process Measurement and Optimization

  6. Other Topics

5. MARCO Gigascale Silicon Research Center: Calibrating Achievable Design Theme

"Calibrating Achievable Design" (C.A.D.)
is a research theme within the MARCO Gigascale Silicon Research Center. The C.A.D. theme encompasses 7 faculty (Wayne Wei-Ming Dai, Andrew Kahng, Tsu-Jae King, Wojciech Maly, Igor Markov, Herman Schmit, Dennis Sylvester), 11 Ph.D. students, and 2 research staff at five schools (CMU, Michigan, UCSC, UCSD, Berkeley); total funding is just over $1M/year. Other research themes within the GSRC formulate and solve aspects of the design problem (or, change the design problem), i.e., they address the "design productivity gap" with platform-based design, silicon implementation platforms, etc. The C.A.D. theme, by contrast, focuses on improving the core technology delivery aspects of EDA.

Within the C.A.D. theme are three initiatives:

  • "Technology Extrapolation": the GSRC Technology Extrapolation system (GTX), a framework for a living roadmap that identifies when key design problems will face the industry;
  • "CAD-IP Reuse": an open-source framework for algorithm implementation reuse that addresses both time-to-market and quality-of-result problems for CAD algorithm and tool researchers and developers; and
  • "Metrics": an open-source framework for instrumentation and measurement of design tools and design processes, aimed at enabling the optimization of tools and processes.

Respectively, these initiatives address three facets of the design technology productivity gap: (1) what are the key design problems?, (2) how can we best develop high-quality solutions?, and (3) did we actually solve those key problems? A future initiative will, we hope, address VLSI / VLSI Design Education using many of the precepts from the CAD-IP Reuse and Metrics initiatives.

  1. The GTX system is discussed under the Technology Extrapolation / Living Roadmap link in our group research projects page.

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  3. The GSRC Bookshelf for Fundamental CAD Algorithms

    Accelerating changes in process technology, system implementation platforms, and electronics markets make future design technology requirements uncertain. A new design technology's time to market - from understanding the design problem to integrating a new solution in mainstream flows - can span several process generations and the life of entire electronics markets. Thus, for designers, obtaining the right design technology at the right time is difficult. This situation demands that the entire design technology community (commercial vendors, captive CAD organizations, and academic researchers) focus on improving the delivery of design technology.

    Today's design technology landscape shows many signs of the design technology productivity gap. Phrases such as "design productivity gap" (e.g., in the International Technology Roadmap for Semiconductors) and the existence of the MARCO Design and Test Focus Research Center reflect a perceived need to improve the effectiveness of CAD-algorithm research. In 1999, the Design Automation Conference found it necessary to institute a new topic area: "Fundamental CAD Algorithms." At a more technical level, research fragmented across too many subcommunities indicates a need to clarify the technological leading edge. And at the level of individual problem formulations (specifically, hypergraph bipartitioning), we have noticed cases of silent, undocumented implementation decisions that change result quality by more than 400%. We also know of two papers published since April 1998 that report more than 1,000% differences in solution costs returned by implementations of the same well-known algorithm. To help the CAD community address these problems, we have developed a new medium for CAD-IP reuse, under the auspices of the MARCO Gigascale Silicon Research Center (http://www.gigascale.org/). Called the MARCO GSRC Bookshelf, it serves as a clearinghouse and a repository for intellectual property in CAD.

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  5. A Metrics System for Design Process Measurement and Optimization

    METRICS encompasses the instrumentation of design tools and design processes, the collection of design artifact and design process data, and the prediction of future results and data based on current information. METRICS seeks to address the improvement of system design and implementation technology (e.g., , flows and methodology) as science, rather than as art.

    A key precept is that measuring a design process is a prerequisite for learning how to optimize it and continuously achieve maximum productivity. The METRICS system enables us to (i) unobtrusively gather characteristics of design artifacts, design processes, and communications during the system development effort, and (ii) analyze and compare that data to analogous data from prior efforts.

    Potential benefits that are enabled by METRICS system include the following.

    • Accurate resource prediction can be made at any point in the design cycle. Based on information from previous design efforts, required resources for a project can be predicted -- including people, time, hardware and tools licenses, etc. Decisions for "go/no go" on the project can be made correctly at the earliest possible point.
    • Projects can be monitored at any given time. With web-based, status-at-a-glance reports, project managers can see the current status of their projects.
    • Elimination of wasted resources that are due to engineers solving the same problem redundantly, at the wrong time in the design process, with too few resources, etc.
    • Realistic data is used for continuous improvement of the design tools and methodologies. There is no longer any need for artificial "benchmarks" or extrapolations.
    • With standardization of design metrics, comparison between designs will be easier. Key design metrics can also be identified so that designers and tool developers can focus their attention more on these important metrics, rather than analyzing vast masses of less important data.

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