UCSD VLSI CAD LABORATORY














Last Modified: October 11, 2006

Topics:

  1. The VLSI Design-Manufacturing Interface
  2. VLSI Interconnect Performance Analysis and Optimization
  3. VLSI Interconnect Synthesis and Prediction
  4. Technology Extrapolation and the "Living Roadmap"
  5. MARCO GSRC Calibrating Achievable Design (C.A.D.) Theme
  6. Other Topics

4. Technology Extrapolation and A Living ITRS (Roadmap)

Technology extrapolation -- i.e., the calibration and prediction of achievable design in future technology generations -- drives the evolution of VLSI system architectures, design methodologies, and design tools. It informs our picture of where and when future hard design issues must arise -- e.g., power/current management, global synchronization, high-speed global signaling, layout on-the-fly -- and how far particular methodologies (i.e., restrictions to the available solution space) will take us in maintaining productivity with acceptable QOR penalty.

The scope of technology extrapolation ranges from device/interconnect modeling to system architecture models and metrics; from top-level wirelength distributions to implications of SOI on delay analysis accuracy. Via roadmapping efforts such as the International Technology Roadmap for Semiconductors (ITRS), technology extrapolation also influences levels of investment in various areas of academic research, private-sector entrepreneurial activity, and other facets of VLSI design automation.

GTX, the MARCO GSRC Technology Extrapolation system, seeks to provide a robust, portable framework for the interactive specification and comparison of alternative modeling choices, e.g., for predicting system cycle time, die size, or power dissipation. Unlike previous "hard-coded" systems, GTX adopts a paradigm wherein parameters and rules allow users to flexibly capture attributes and relationships germane to VLSI technology and design. Serialized user-defined rules can be composed in numerous ways to define rule chains, which are then executed by a derivation engine to perform studies. Supporting grammars, parameter naming conventions, extension mechanisms, etc. enable GTX to incorporate -- and serve as a repository for -- literally unlimited forms of domain knowledge.

GTX intends to meld the rich heritage of VLSI technology extrapolation originated by Bakoglu/Meindl (SUSPENS), Sai-Halasz, GENESYS, RIPE, BACPAC, etc. with the paradigm of flexibility established in the AI constraint programming and design support literatures (DesignSheet, UniCalc/NeMo, etc.), along with improved optimization and visualization capabilities. GTX objectives include the following.

  • Examination of all "rules" and modeling choices in recent influential VLSI technology extrapolation systems (BACPAC, RIPE, GENESYS), with an aim to characterizing both modeling sensitivities and parameter sensitivities.

  • Integration of better models of the consequences of heuristic optimizations that are inherent in the design process, e.g., optimized multi-terminal global interconnects, optimized floorplans, optimized embeddings, optimized area routings on multi-layer interconnect resources, etc. To this end, GTX supports several flavors of "rules", include code, ASCII (closed-form equation), and external executable rules.

  • Careful consideration of usability (portability and data security, in-line user-extensibility, facilities for optimization and trade studies, etc.).

  • Extensions beyond existing technology extrapolation efforts via new rule modules to capture manufacturing variability, reliability, novel technologies (SOI, MTCMOS), various objectives (e.g., power or cost), etc. GTX can also serve as a unified repository for calibration data and "technology files".

  • Energy and long-term commitment to the creation of a "Living ITRS" as well as a "living roadmap for EDA": living, growing frameworks for technology extrapolation that support roadmapping needs and technology investment decisions into the future.

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