UCSD VLSI CAD LABORATORY














Last Modified: October 11, 2006

Topics:

  1. The VLSI Design-Manufacturing Interface
  2. VLSI Interconnect Performance Analysis and Optimization
    1. Estimates of Crosstalk-Induced Delay Variation
    2. Layout-Based Solutions for Signal Integrity
  3. VLSI Interconnect Synthesis
  4. Technology Extrapolation and the "Living Roadmap"
  5. MARCO GSRC Calibrating Achievable Design (C.A.D.) Theme
  6. Other Topics

2. VLSI Interconnect Performance Analysis and Optimization
  1. Estimates of Crosstalk-Induced Delay Variation

    Capacitive crosstalk in interconnect is the major contributor to signal delay and causes various signal integrity problems. We are re-assessing the classic switch-factor based methodology for estimation of delay impact of crosstalk. (Puneet Gupta)

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  3. Layout-Based Solutions for Signal Integrity

    Two trends motivate the following work. First, as the number of routing layers increases, the cost (via parasitics, via reliability, via blockage effects) of buffer insertion also increases. Second, as the integration of hard IP or noise-sensitive blocks in the SOC context increases, it is again more difficult to insert buffers into global interconnect on an as-needed basis. Our work investigates the problem of capacitive crosstalk, and considers the tradeoffs inherent in various "pure routing" solutions. One well-known example of such a solution is "swizzling" (i.e., permuting) parallel wires of a wide global bus so that no pair of wires will experience worst-case coupling for more than some fixed length.

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