**Alternative Mask Writing Strategies**
Mask writing is an increasingly critical and costly step in the
semiconductor manufacturing flow. Rapid technology scaling and the
aggressive use of reticle enhancement techniques in subwavelength optical
lithography lead to stringent tolerances for mask critical dimensions
(CD). Ever-decreasing feature sizes are achieved today using high-resolution,
variable shaped electron-beam writers. However, CD control becomes more
challenging, especially as mask CD errors can be "amplified" during
exposure, development and etch of chemically amplified resists (cf. the
"mask error enhancement factor" (MEEF)).

Resist heating is a phenomenon that arises during e-beam write and affects
CD accuracy of masks. It is estimated that resist heating during
mask write alone contributes between 10-20% of the total
lithographic CD error in the 180nm technology node. Thus, heating effects
may prove to be a serious obstacle to efficient mask fabrication at future
technology nodes. In this work, we develop a writing approach that
differs from the conventional Vector Scan Beam (VSB), in that its goal is
to minimize the maximum accumulated temperature over the reticle. In this
writing approach, the objectives are two-fold: (1)maximize the distance
between subfields written at times t and t + i, for i = 1, 2,.., k, and
(2) minimize the total write time of the mask.

This formulation is, in effect, a "self-avoiding traveling salesman problem"
(SA-TSP): it modifies the classical TSP problem by adding the
constraint that the tour avoids recently visited locations.
The self-avoiding property minimizes the impact of resist heating, while
the traveling salesman objective of minimum tour cost minimizes total
write time. We have developed heuristics for the SA-TSP problem on
finite grids, and we are now seeking to verify the utility of
corresponding writing approaches through finite-element analysis of
thermal patterns in resist (using a mask heating model developed
with ABAQUS).