UCSD VLSI CAD LABORATORY














Last Modified: June 24, 2015
Many of the papers below have been made available in PDF format for easy access. Please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.
Publications
Conference Papers
  1. A. B. Kahng, "Fast Hypergraph Partition", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1989, pp. 762-766. 
  2. A. B. Kahng, "Traveling Salesman Heuristics and Embedding Dimension in the Hopfield Model", (.ps), (.pdf), Proc. IEEE/INNS Intl. Joint Conf. on Neural Networks, June 1989, pp. I-513 - I-520. 
  3. A. B. Kahng and G. Robins, "A New Class of Steiner Tree Heuristics with Good Performance: the Iterated 1-Steiner Approach", (.ps), (.pdf), Proc. IEEE International Conf. on Computer-Aided Design, November 1990, pp. 428-431 (Distinguished Paper Award; 18 awards out of 442 submissions). 
  4. A. B. Kahng, J. Cong and G. Robins, "High-Performance Clock Routing Based on Recursive Geometric Matching", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1991, pp. 322-327. 
  5. A. B. Kahng, "A Steiner Tree Construction for VLSI Routing", (.ps), (.pdf), Proc. IEEE/INNS Intl. Joint Conf. on Neural Networks, July 1991, pp. I-133 - I-139. 
  6. A. B. Kahng and G. Robins, "Optimal Algorithms for Determining Regularity in Pointsets", Proc. Third Canadian Conf. on Computational Geometry, August 1991, pp. 167-170. 
  7. J. Cong, L. Hagen and A. B. Kahng, "Random Walks for Circuit Clustering", (.ps), (.pdf), Proc. 4th IEEE Intl. ASIC Conf., September 1991, pp. 14.2.1 - 14.2.4. 
  8. J. Cong, A. B. Kahng and G. Robins, "On Clock Routing For General Cell Layouts", (.ps), (.pdf), Proc. 4th IEEE Intl. ASIC Conf., September 1991, pp. 14.5.1 - 14.5.4. 
  9. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, "Performance-Driven Global Routing for Cell Based IC's", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Computer Design, October 1991, pp. 170-173. 
  10. A. B. Kahng, "An Effective Analog Approach to Steiner Routing", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Computer Design, October 1991, pp. 166-169. 
  11. L. Hagen and A. B. Kahng, "Fast Spectral Methods for Ratio Cut Partitioning and Clustering", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1991, pp. 10-13. 
  12. A. B. Kahng, "Exploiting Fractalness in Error Surfaces: New Methods for Neural Network Learning", (.ps), (.pdf), Proc. IEEE Intl. Symp. on Circuits and Systems, May 1992, pp. 41-44. 
  13. A. B. Kahng, G. Robins and E. Walkup, "New Results and Algorithms for MCM Substrate Testing", (.ps), (.pdf), Proc. IEEE Intl. Symp. on Circuits and Systems, May 1992, pp. 1113-1116. 
  14. J. Cong, A. B. Kahng, G. Robins, M. Sarrafzadeh and C. K. Wong, "Provably Good Algorithms for Performance-Driven Global Routing", (.ps), (.pdf), Proc. IEEE Intl. Symp. on Circuits and Systems, May 1992, pp. 2240-2243. 
  15. K. C. Chen, J. Cong, A. Kahng and P. Trajmar, "DAG-MAP: Graph Based FPGA Technology Mapping for Delay Optimization", Proc. IEEE Workshop on Field-Programmable Gate Arrays, March 1992, pp. 77-81. 
  16. A. B. Kahng, "Random Structure of Error Surfaces: Toward New Stochastic Learning Methods", invited paper, (.ps), (.pdf), Proc. SPIE (Joint Conf. on Artificial Neural Networks: Science and Applications), 1710 (pt. 1, vol. 2) April 1992, pp. 768-779. 
  17. J. Cong, L. Hagen and A. B. Kahng, "Net Partitions Yield Better Module Partitions", (.ps), (.pdf), Proc. 29th ACM/IEEE Design Automation Conf., June 1992, pp. 47-52 (nominated for Best Paper Award; 18 nominees out of 440 submissions). 
  18. L. Hagen, A. B. Kahng, F. Kurdahi and C. Ramachandran, "On the Intrinsic Rent Parameter and New Spectra-Based Methods for Wireability Estimation", (.ps), (.pdf), Proc. European Design Automation Conf., October 1992, pp. 202-208 (nominated for Best Paper Award; 6 nominees out of 335 submissions). 
  19. K. C. Chen, Y. Ding, J. Cong, A. Kahng and P. Trajmar, "An Improved Graph Based FPGA Technology Mapping Algorithm for Delay Optimization", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Computer Design, October 1992, pp. 154-158. 
  20. K. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees With Minimum Wirelength", (.ps), (.pdf), Proc. IEEE 5th Intl. ASIC Conf., September 1992, pp. 1.1.1 - 1.1.5. 
  21. L. Hagen and A. B. Kahng, "Improving the Quadratic Objective Function in Module Placement", (.ps), (.pdf), Proc. IEEE 5th Intl. ASIC Conf., September 1992, pp. 1.7.1 - 1.7.4. 
  22. L. Hagen and A. B. Kahng, "A New Approach to Effective Circuit Clustering", (.ps), (.pdf) Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1992, pp. 422-427. 
  23. K. D. Boese, J. Cong, A. B. Kahng, K. S. Leung and D. Zhou, "On High-Speed VLSI Interconnects: Analysis and Design", (.ps), (.pdf) Proc. Asia-Pacific Conf. on Circuits and Systems, December 1992, pp. 35-40. 
  24. K. D. Boese and A. B. Kahng, "Simulated Annealing of Neural Networks: the 'Cooling' Strategy Revisited", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Circuits and Systems, May 1993, pp. 2572-2575. 
  25. C. J. Alpert, J. Cong, A. B. Kahng, G. Robins and M. Sarrafzadeh, "Minimum Density Interconnection Trees", (.ps), (.pdf) Proc. IEEE Intl. Conf. on Circuits and Systems, May 1993, pp. 1865-1868. 
  26. C. J. Alpert, T. C. Hu, J. H. Huang and A. B. Kahng, "A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-Driven Global Routing", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Circuits and Systems, May 1993, pp. 1869-1872. 
  27. C. J. Alpert and A. B. Kahng, "Geometric Embeddings for Faster (and Better) Multi-Way Netlist Partitioning", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1993, pp. 743-748. 
  28. K. D. Boese, A. B. Kahng and G. Robins, "High-Performance Routing Trees With Identified Critical Sinks", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1993, pp. 182-187. 
  29. K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, "Toward Optimal Routing Trees", (.ps), (.pdf), Proc. ACM SIGDA Physical Design Workshop, April 1993, pp. 44-51. 
  30. K. D. Boese, A. B. Kahng and C.-W. A. Tsao, "Best-So-Far vs. Where-You-Are: New Perspectives on Simulated Annealing for CAD", (.ps), (.pdf), Proc. European Design Automation Conf., September 1993, pp. 78-83. 
  31. K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, "Fidelity and Near-Optimality of Elmore-Based Routing Constructions", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Computer Design, October 1993, pp. 81-84. 
  32. C. J. Alpert and A. B. Kahng, "Multi-Way Partitioning Via Spacefilling Curves and Dynamic Programming", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 652-657. (Best Paper Award out of 439 submissions.) 
  33. A. B. Kahng and S. Muddu, "Delay Analysis of VLSI Interconnections Using the Diffusion Equation Model", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 563-569. 
  34. K. D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, "Rectilinear Steiner Trees with Minimum Elmore Delay", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 381-386. 
  35. A. B. Kahng and S. Muddu, "Optimal Equivalent Circuits for Interconnect Delay Calculations Using Moments", (.ps), (.pdf), Proc. European Design Automation Conference, September 1994, pp. 164-169. 
  36. A. B. Kahng and C.-W. A. Tsao, "Planar-DME: Improved Planar Zero-Skew Clock Routing with Minimum Pathlength Delay", (.ps), (.pdf), Proc. European Design Automation Conference, September 1994, pp. 440-445. (Nominated for Best Paper Award; 7 nominees out of 260 submissions.) 
  37. A. B. Kahng and C.-W. A. Tsao, "Low-Cost Planar Clock Trees With Exact Zero Elmore Delay Skew", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1994, pp. 213-218. 
  38. C. J. Alpert and A. B. Kahng, "A General Framework for Vertex Orderings, With Applications to Netlist Clustering", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1994, pp. 63-67. 
  39. A. B. Kahng and S. Muddu, "Two-Pole Analysis of Interconnection Trees", (.ps), (.pdf), Proc. IEEE Multi-Chip Module Conference, February 1995, pp. 105-110. 
  40. J. H. Huang and A. B. Kahng, "Multi-Way System Partitioning into a Single Type or Multiple Types of FPGAs", (.ps), (.pdf), Proc. ACM Intl. Symp. on Field-Programmable Gate Arrays, February 1995, pp. 140-145. 
  41. J. H. Huang and A. B. Kahng, "When Clusters Meet Partitions: New Density-Based Methods for Circuit Decomposition", (.ps), (.pdf), Proc. European Design and Test Conference, March 1995, pp. 60-64. 
  42. K. D. Boese, D. E. Franklin and A. B. Kahng, "Training Minimal Artificial Neural Network Architectures for Subsoil Object Detection", (.ps), (.pdf), Proc. SPIE Aerosense-95: Detection Technologies for Mines and Minelike Targets, April 1995, pp. 900-911. 
  43. D. E. Franklin, A. B. Kahng and M. A. Lewis, "Distributed Sensing and Probing With Multiple Search Agents: Toward System-Level Landmine Detection Solutions", (.ps), (.pdf), Proc. SPIE Aerosense-95: Detection Technologies for Mines and Minelike Targets, April 1995, pp. 698-709. 
  44. L. Hagen, J. H. Huang and A. B. Kahng, "Quantified Suboptimality of VLSI Layout Heuristics", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1995, pp. 216-221. 
  45. J. H. Huang, A. B. Kahng and C.-W. A Tsao, "On the Bounded-Skew Clock and Steiner Routing Problems", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1995, pp. 508-513. 
  46. Y. Cao, T.-W. Chen, M. Harris, A. B. Kahng, M. A. Lewis and A. D. Stechert, "A Remote Robotics Laboratory on the Internet", (.ps), (.pdf), Proc. INET-95, June 1995, pp. 65-72. 
  47. A. B. Kahng and B. R. Moon, "Toward More Powerful Recombinations", (.ps), (.pdf), Proc. Intl. Conf. on Genetic Algorithms, July 1995, pp. 96-103. 
  48. Y. Cao, A. S. Fukunaga, A. B. Kahng and F. Meng, "Cooperative Mobile Robotics: Antecedents and Directions", (.ps), (.pdf), Proc. IEEE/RSJ Intl. Symp. on Intelligent Robotics and Systems, August 1995, pp. 226-234. 
  49. L. Hagen, J. H. Huang and A. B. Kahng, "On Implementation Choices for Iterative Improvement Partitioning Algorithms", (.ps), (.pdf), Proc. European Design Automation Conf., September 1995, pp. 144-149. 
  50. J. Cong, A. B. Kahng, C. K. Koh and C.-W. A. Tsao, "Bounded-Skew Clock and Steiner Routing Under Elmore Delay", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Computer-Aided Design, November 1995, pp. 66-71. 
  51. A. S. Fukunaga and A. B. Kahng, "Improving the Performance of Evolutionary Optimization by Dynamically Scaling the Evaluation Function", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Evolutionary Computation, November 1995, pp. I-182 - I-187. 
  52. I. Hong, A. B. Kahng and B. R. Moon, "Exploiting Synergies of Multiple Crossovers: Initial Studies", (.ps), (.pdf), Proc. IEEE Intl. Conf. on Evolutionary Computation, November 1995, pp. I-245 - I-250. 
  53. A. B. Kahng and S. Muddu, "Efficient Gate Delay Modeling for Large Interconnect Loads", (.ps), (.pdf), Proc. IEEE Multi-Chip Module Conference, February 1996, pp. 202-207. 
  54. C. J. Alpert, L. Hagen and A. B. Kahng, "A Hybrid Multilevel/Genetic Approach for Circuit Partitioning", (.ps), (.pdf), Proc. ACM SIGDA Physical Design Workshop, April 1996, pp. 100-105. 
  55. A. B. Kahng and S. Muddu, "An Analytical Delay Model for RLC Interconnects", (.ps), (.pdf), Proc. IEEE Intl. Symp. on Circuits and Systems, May 1996, pp. IV/237-240. 
  56. A. B. Kahng and S. Muddu, "New Analyses of Distributed RC Interconnections", (.ps), (.pdf), Proc. IEEE Intl. Symp. on Circuits and Systems, May 1996, pp. IV/241-244. 
  57. A. S. Fukunaga, J. H. Huang and A. B. Kahng, "Large-Step Markov Chain Variants for VLSI Netlist Partitioning", (.ps), (.pdf), Proc. IEEE Intl. Symp. on Circuits and Systems, May 1996, pp. IV/496-499. 
  58. C. J. Alpert and A. B. Kahng, "Simple Eigenvector-Based Circuit Clustering Can Be Effective", (.ps), (.pdf), Proc. IEEE Intl. Symp. on Circuits and Systems, May 1996, pp. IV/683-686. 
  59. A. B. Kahng and S. Muddu, "Analysis of RC Interconnections Under Ramp Input", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conference, June 1996, pp. 533-538. 
  60. A. B. Kahng, K. Masuko and S. Muddu, "Analytical Delay Models for VLSI Interconnections Under Ramp Input", (.ps), (.pdf), Proc. ACM/IEEE Intl. Conference on Computer-Aided Design, November 1996, pp. 30-36. 
  61. A. B. Kahng and S. Muddu, "Delay Analysis of Coupled Transmission Lines", (.ps), (.pdf), Proc. Asia-Pacific Conference on Circuits and Systems, November 1996, pp. 81-84. 
  62. A. B. Kahng and S. Muddu, "Gate Load Delay Computation Using Analytical Models", (.ps), (.pdf), Proc. Asia-Pacific Conference on Circuits and Systems , November 1996, pp. 433-436. 
  63. C. J. Alpert, L. W. Hagen and A. B. Kahng, "A Hybrid Multilevel/Genetic Approach for Circuit Partitioning", (.ps), (.pdf), Proc. Asia-Pacific Conference on Circuits and Systems, November 1996, pp. 298-301. 
  64. A. B. Kahng, K. Masuko and S. Muddu, "Delay Models for MCM Interconnects When Response is Non-Monotone", (.ps), (.pdf), Proc. IEEE Multi-Chip Module Conference, March 1997, pp. 102-107. 
  65. C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet and K. Yan, "Faster Minimization of Linear Wirelength for Global Placement", (.ps), (.pdf), (slides), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1997, pp. 4-11. 
  66. D. J. Huang and A. B. Kahng, "Partitioning-Based Standard-Cell Global Placement with an Exact Objective", (.ps), (.pdf), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1997, pp. 18-25. 
  67. J. Cong, A. B. Kahng and K.-S. Leung, "Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence Problem with Applications to VLSI Physical Design", (.ps), (.pdf), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1997, pp. 88-95. 
  68. C. J. Alpert, D. J. Huang and A. B. Kahng, "Multilevel Circuit Partitioning", (.ps), (.pdf), (slides), Proc. ACM/IEEE Design Automation Conference, June 1997, pp. 530-533. 
  69. J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali and S. H.-C. Yen, "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", (.ps), (.pdf), (slides), Proc. ACM/IEEE Design Automation Conference, June 1997, pp. 627-632. 
  70. A. B. Kahng and C.-W. A. Tsao, "More Practical Bounded-Skew Clock Routing", (.ps), (.pdf), (slides), Proc. ACM/IEEE Design Automation Conference, June 1997, pp. 594-599. 
  71. C. J. Alpert, T. Chan, D. J.-H. Huang, I. Markov and K. Yan, "Quadratic Placement Revisited", (.ps), (.pdf), (slides), Proc. ACM/IEEE Design Automation Conference, June 1997, pp. 752-757. 
  72. W. Huang and A. B. Kahng, "A Layout Advisor for Timing-Critical Bus Routing", (.ps), (.pdf), (slides), Proc. IEEE ASIC Conference, September 1997, pp. 210-214. 
  73. A. B. Kahng, S. Muddu, E. Sarto and R. Sharma, "Interconnect Tuning Strategies for High-Performance ICs", (.ps), (.pdf), (slides), Proc. Design, Automation and Test in Europe, February 1998. 
  74. A. E. Caldwell, A. B. Kahng, S. Mantik and I. L. Markov, "Implications of Area-Array I/O for Row-Based Placement Methodology", (.ps), (.pdf), (slides), Proc. IEEE Symp. on IC/Package Design Integration, February 1998, pp. 93-98. 
  75. A. B. Kahng, G. Robins, A. Singh, H. Wang and A. Zelikovsky, "Filling and Slotting: Analysis and Algorithms", (.ps), (.pdf), (slides), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1998, pp. 95-102. 
  76. A. B. Kahng and S. Muddu, "New Efficient Algorithms for Computing Effective Capacitance", (.ps), (.pdf), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1998, pp. 147-151. 
  77. A. B. Kahng, "Futures for Partitioning in Physical Design", (.ps), (.pdf), (slides), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1998, pp. 190-193. 
  78. A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement", (.ps), (.pdf), (slides), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 1998, pp. 4-11. 
  79. A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, "Watermarking Techniques for Intellectual Property Protection" (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conference, June 1998, pp. 776-781. 
  80. A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang and G. Wolfe, "Robust IP Watermarking Methodologies for Physical Design", (.ps), (.pdf), (slides), Proc. ACM/IEEE Design Automation Conference, June 1998, pp. 782-787. 
  81. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Relaxed Partitioning Balance Constraints in Top-Down Placement", (.ps), (.pdf), (slides), Proc. IEEE ASIC Conference, September 1998, pp. 229-232. 
  82. A. B. Kahng, H. Wang and A. Zelikovsky, "Automated Layout and Phase Assignment Techniques for Dark Field Alternating PSM", (.ps), (.pdf), (.ppt), Proc. 18th BACUS Symposium on Photomask Technology and Management, September 1998, pp. 222-231.
  83. A. B. Kahng, "IC Layout and Manufacturability: Critical Links and Design Flow Implications", (.ps), (.pdf), (slides), Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 100-105.
  84. A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky, "New and Exact Filling Algorithms for Layout Density Control", (.ps), (.pdf), (slides), Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 106-110.
  85. A. B. Kahng, S. Muddu, E. Sarto, "Interconnect Optimization Strategies for High-Performance VLSI Design", (.ps), (.pdf), Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 464-469.
  86. A. B. Kahng and S. Muddu, "Improved Effective Capacitance Computations for Use in Logic and Layout Optimization", (.ps), (.pdf), (slides), Proc. IEEE Intl. Conf. on VLSI Design, Jan. 1999, pp. 578-582.
  87. A. B. Kahng, G. Robins, A. Singh and A. Zelikovsky, "New Multilevel and Hierarchical Algorithms for Layout Density Control", (.ps), (.pdf), Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 221-224.
  88. R. Baldick, A. B. Kahng, A. Kennings and I. L. Markov, "Function Smoothing with Applications to VLSI Layout", (.ps), (.pdf), (slides), Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 225-228. (Nominated for Best Paper award).
  89. A. B. Kahng , P. Tucker and A. Zelikovsky, "Optimization of Linear Placements for Wirelength Minimization with Free Sites", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 1999, pp. 241-244. (Nominated for Best Paper award).
  90. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning", (.ps), (.pdf), (slides), Proc. Workshop on Algorithm Engineering and Experimentation (ALENEX), Jan. 1999, pp. 177-193 
  91. P. Berman, A. B. Kahng, D. Vidhani, H. Wang and A. Zelikovsky, "Optimal Phase Conflict Removal for Layout of Dark Field Alternating Phase Shifting Masks", (.ps), (.pdf), (slides), Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 121-126.
  92. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Optimal Partitioners and End-Case Placers for Standard-Cell Layout", (.ps), (.pdf), (slides), Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 90-96.
  93. C. J. Alpert, A. E. Caldwell, A. B. Kahng and I. L. Markov, "Partitioning With Terminals: A 'New' Problem and New Benchmarks", (.ps), (.pdf), (slides), Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 151-157.
  94. A. B. Kahng and Y. C. Pati, "Subwavelength Optical Lithography: Challenges and Impact on Physical Design", (.ps), (.pdf), (slides), Proc. ACM Intl. Symp. on Physical Design, April 1999, pp. 112-119.
  95. A. E. Caldwell, A. B. Kahng, A. A. Kennings and I. L. Markov, "Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 349-354.
  96. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Hypergraph Partitioning with Fixed Vertices", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 355-359.
  97. A. E. Caldwell, H.-J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak and G. Qu, "Effective Iterative Techniques for Fingerprinting Design IP", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 843-848.
  98. A. B. Kahng and Y. C. Pati, "Subwavelength Lithography and its Potential Impact on Design and EDA", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 1999, pp. 799-804.
  99. P.Berman, A. B. Kahng, D. Vidhani and A. Zelikovsky, "The T-Join Problem in Sparse Graphs: Applications to Phase Assignment Problem in VLSI Mask Layout", (.ps), (.pdf), Proc. Workshop on Algorithms and Data Structures (WADS), LNCS(vol. 1663), August 1999, pp. 25-36.
  100. A. B. Kahng, S. Muddu and D. Vidhani, "Noise and Delay Uncertainty Studies for Coupled RC Interconnects", (.ps), (.pdf), (.ppt), Proc. IEEE International ASIC/SOC Conference, September 1999, pp. 3-8.
  101. Y. Chen, A. B. Kahng, G. Qu and A. Zelikovsky, "The Associative-Skew Clock Routing Problem", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 1999, pp. 168-172.
  102. A. B. Kahng, D. Kirovski, S. Mantik, M. Potkonjak and J. L. Wong, "Copy Detection for Intellectual Property Protection of VLSI Design", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 1999, pp. 600-604.
  103. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Improved Algorithms for Hypergraph Bipartitioning", (.ps), (.pdf), (slides), Proc. Asia and South Pacific Design Automation Conf., Jan. 2000, pp. 661-666. 
  104. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Monte-Carlo Algorithms for Layout Density Control", (.ps), (.pdf), (slides), Proc. Asia and South Pacific Design Automation Conf., Jan. 2000, pp. 523-528. 
  105. A. B. Kahng, S. Mantik and D. Stroobandt, "Requirements for Models of Achievable Routing", (.ps), (.pdf), (.ppt), Proc. ACM Intl. Symp. on Physical Design, April 2000, pp. 4-11.
  106. A. B. Kahng, "Classical Floorplanning Harmful?", (.ps), (.pdf), (.ppt), Proc. ACM Intl. Symp. on Physical Design, April 2000, pp. 207-213.
  107. A. B. Kahng and D. Stroobandt, "Wiring Layer Assignments with Consistent Stage Delays", (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, April 2000, pp. 115-122.
  108. A. B. Kahng, S. Muddu and E. Sarto, "On Switch Factor Based Analysis of Coupled RC Interconnects", (.ps), (.pdf), Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 79-84.
  109. A. E. Caldwell, A. B. Kahng and I. L. Markov, "Can Recursive Bisection Alone Produce Routable Placements?", (.ps), (.pdf), ((.ppt), Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 477-482.
  110. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Practical Iterated Fill Synthesis for CMP Uniformity", (.ps), (.pdf), ((.ppt), Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 671-674.
  111. A. E. Caldwell, Y Cao, A. B. Kahng, F. Koushanfar, H. Lu, I. L. Markov, M. R. Oliver, D. Stroobandt and D. Sylvester, "GTX: The MARCO GSRC Technology Extrapolation System", (.ps), (.pdf), ((.ppt), Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 693-698.
  112. S. Fenstermaker, D. George, A. B. Kahng, S. Mantik and B. Thielges, "METRICS: A System Architecture for Design Process Optimization", (.ps), (.pdf), ((.ppt), Proc. ACM/IEEE Design Automation Conf., June 2000, pp. 705-710.
  113. A. B. Kahng and S. Mantik, "On Mismatches Between Incremental Optimizers and Instance Perturbations in Physical Design Tools", (.ps), (.pdf), ((.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2000, pp. 17-21. 
  114. Y. Cao, C. M. Hu, X. J. Huang, A. B. Kahng, S. Muddu, D. Stroobandt and D. Sylvester, "Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design", (.ps), (.pdf), ((.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2000, pp. 56-61. 
  115. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably Good Global Buffering Using an Available Buffer Block Plan", (.ps), (.pdf), ((.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2000, pp. 104-109.
  116. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Hierarchical Dummy Fill for Process Uniformity", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2001, pp. 139-144. 
  117. C. K. Cheng, A. B. Kahng, B. Liu and D. Stroobandt, "Toward Better Wireload Models in the Presence of Obstacles", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2001, pp. 527-532. 
  118. A. B. Kahng, S. Vaya and A. Zelikovsky, "New Graph Bipartizations for Double-Exposure, Bright Field Alternating Phase-Shift Mask Layout", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2001, pp. 133-138. 
  119. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky, "Provably Good Global Buffering by Multiterminal Multicommodity Flow Approximation", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2001, pp. 120-125. 
  120. A. B. Kahng, "Design Technology Productivity in the DSM Era", (.ps), (.pdf), invited paper, Proc. Asia and South Pacific Design Automation Conf., Jan. 2001, pp. 443-448.
  121. A. B. Kahng, S. Muddu, N. Pol and D. Vidhani, "Noise Model for Multiple Segmented Coupled RC Interconnects", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality in Electronic Design , March 2001, pp. 145-150.
  122. A. B. Kahng and S. Mantik, "A System for Automatic Recording and Prediction of Design Quality Metrics", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality in Electronic Design, March 2001, pp. 81-86. (Best Paper Award).
  123. C. K. Cheng, A. B. Kahng and B. Liu, "Interconnect Implications of Growth-Based Structural Models for VLSI Circuits", (.ps), (.pdf), (.ppt) , Proc. ACM International Workshop on System-Level Interconnect Prediction, April 2001, pp. 99-106.
  124. K. D. Boese, A. B. Kahng and S. Mantik, "On the Relevance of Wire Load Models", (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, April 2001, pp. 91-98.
  125. C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu, S. T. Quay, S. S. Sapatnekar, A. J. Sullivan and P. Villarrubia, "Buffered Steiner Trees for Difficult Instances", (.ps), (.pdf), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2001, pp. 4-9. 
  126. F. Dragan, A. B. Kahng, I. Mandoiu, S. Muddu and A. Zelikovsky, "Practical Approximation Algorithms for Separable Packing Linear Programs", (.ps), (.pdf), (.ppt), Proc. 7th International Workshop on Algorithms and Data Structures, August 2001, pp. 325-337. 
  127. C. Albrecht, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky, "On the Skew-Bounded Minimum Buffer Routing Tree Problem", (.ps), (.pdf), (.ppt), Proc. The Tenth Workshop on Synthesis And System Integration of Mixed Technologies, October 2001, pp. 250-256. 
  128. A. B. Kahng, R. Kastner, S. Mantik, M. Sarrafzadeh, and X. Yang, "Studies of Timing Structural Properties for Early Evaluation of Circuit Design", (.ps), (.pdf), (.ppt), Proc. The Tenth Workshop on Synthesis and System Integration of Mixed Technologies, October 2001, pp. 285-292.
  129. C. J. Alpert, A. B. Kahng, B. Liu, I. Mandoiu and A. Zelikovsky, "Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control", (.ps), (.pdf), (.ppt), Proc. IEEE-ACM Intl. Conf. on Computer-Aided Design, November 2001, pp. 408-415.
  130. C. Albrecht, A. B. Kahng, I. Mandoiu and A. Zelikovsky, "Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment, and Buffer/Wire Sizing", (.ps), (.pdf), (.ppt), Proc. Intl. Conf. on VLSI Design/ASPDAC, January 2002, pp. 580-587. (Best Paper Award out of 269 submissions).
  131. A. Kahng and S. Mantik, "Measurement of Inherent Noise in EDA Tools", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality in Electronic Design, March 2002, pp. 206-211.
  132. A. Kahng and G. Smith, "A New Design Cost Model for the 2001 ITRS", (.ps), (.pdf), Proc. International Symposium on Quality Electronic Design, March 2002, pp. 190-193.
  133. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Monte-Carlo Methods for Chemical-Mechanical Planarization on Multiple-Layer and Dual-Material Models", (.ps), (.pdf), (.ppt), Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, Santa Clara, March 2002, pp. 421-432.
  134. A. B. Kahng, "Design-Process Integration and Shared Red Bricks", (.ps), (.pdf), Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, Santa Clara, March 2002, pp. 390-400.
  135. Y. Chen, A. B. Kahng, G. Robins and A. Zelikovsky, "Closing the Smoothness and Uniformity Gap in Area Fill Synthesis", (.ps), (.pdf), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2002, pp. 137-142.
  136. A. B. Kahng, S. Mantik and I. L. Markov, "Min-Max Placements for Large-Scale Timing Optimization", (.ps), (.pdf), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2002, pp. 143-148.
  137. A. B. Kahng, "A Roadmap and Vision for Physical Design", (.ps), (.pdf), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2002, pp. 112-117.
  138. C. Bandela, Y. Chen, A. B. Kahng, I. I. Mandoiu and A. Zelikovsky, "Auctions with Buyer Preferences", (.ps), (.pdf), Information Systems: The E-Business Challenge - Proc. 17th IFIP World Computer Congress, Kluwer Academic Publishers, 2002, pp. 221-238.
  139. Y. Cao, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, "Design Sensitivities to Variability: Extrapolation and Assessments in Nanometer VLSI", (.ps), (.pdf), Proc. IEEE ASIC/SoC Conference, September 2002, pp. 411-415.
  140. A. B. Kahng, I. I. Mandoiu, P. A. Pevzner, S. Reda, and A. Z. Zelikovsky, "Border Length Minimization in DNA Array Design", (.ps), (.pdf), (.ppt), Proc. 2nd Workshop on Algorithms in Bioinformatics (WABI), September 2002, pp. 435-448.
  141. A. B. Kahng, B. Liu, and I. I. Mandoiu, "Non-Tree Routing for Reliability and Yield Improvement", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2002, pp. 260-266.
  142. A. B. Kahng, I. I. Mandoiu, and A. Zelikovsky, "Highly Scalable Algorithms for Rectilinear and Octilinear Steiner Trees", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2003, pp. 827-833.
  143. P. Gupta, A. B. Kahng and S. Mantik, "Routing-Aware Scan Chain Ordering", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2003, pp. 857-862.
  144. A. B. Kahng and B. Liu, "Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization", (.ps), (.pdf), Proc. IEEE Comp. Soc. Annual Symp. On VLSI, Feb. 2003, pp. 183-188.
  145. A. B. Kahng, R. Ellis, and Y. Zheng, "Compression Algorithms for Dummy Fill VLSI Layout Data", (.ps), (.pdf), (.ppt), Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb. 2003, pp. 233-245.
  146. Y. Chen, P. Gupta, and A. B. Kahng, "Performance-Impact Limited Area Fill Synthesis", (.ps), (.pdf), (.ppt), Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb. 2003, pp. 75-86.
  147. D. Sylvester, P. Gupta, A. B. Kahng, and J. Yang, "Toward Performance-Driven Reduction of the Cost of RET-Based Lithography Control" (Invited Paper) (.ps), (.pdf), (.ppt), Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb. 2003, pp. 123-133.
  148. S. V. Babin, A. B. Kahng, I. I. Mandoiu, and S. Muddu, "Subfield Scheduling for Throughput Maximization in Electron-Beam Photomask Fabrication", (.ps), (.pdf), (.ppt), Emerging Lithographic Technologies VII, R. L. Engelstad (ed.), Proc. SPIE #5037, Feb. 2003, pp. 934-942.
  149. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. H. Zheng, "Area Fill Generation with Inherent Data Volume Reduction", (.ps), (.pdf), (.ppt), Proc. Design, Automation and Test in Europe, March 2003, pp. 868-873.
  150. P. Dasgupta, A. B. Kahng, and S. Muddu, "A Novel Metric for Interconnect Architecture Performance", (.ps), (.pdf), (.ppt), Proc. Design, Automation and Test in Europe, March 2003, pp. 448-453.
  151. P. Gupta and A. B. Kahng, "Quantifying Error in Dynamic Power Estimation of CMOS Circuits", (.ps), (.pdf), (slides), Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 273-278.
  152. P. Gupta, A. B. Kahng and S. Mantik, "A Proposal for Routing-Based Timing-Driven Scan Chain Ordering", (.ps), (.pdf), (.ppt), Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 339-343.
  153. A. B. Kahng and I. L. Markov, "Impact of Interoperability on CAD-IP Reuse: An Academic Viewpoint", (.ps), (.pdf), Proc. IEEE Intl. Symp. on Quality Electronic Design, March 2003, pp. 208-213.
  154. H. Chen, C. K. Cheng, A. B. Kahng, I. Mandoiu and Q. Wang, "Estimation of Wirelength Reduction for λ-Geometry vs. Manhattan Placement and Routing", (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, April 2003, pp. 71-76.
  155. A. B. Kahng and X. Xu, "Accurate Pseudo-Constructive Wirelength and Congestion Estimation", (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, April 2003, pp. 61-68.
  156. A. B. Kahng, "Research Directions for Coevolution of Rules and Routers", (.ps), (.pdf), invited paper, Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2003, pp. 122-125.
  157. A. B. Kahng and X. Xu, "Local Unidirectional Bias for Smooth Cutsize-Delay Tradeoff in Performance-Driven Bipartitioning", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2003, pp. 81-86.
  158. A. B. Kahng, I. Mandoiu, P. Pevzner, S. Reda, and A. Zelikvosky, " Engineering a Scalable Placement Heuristic for DNA Probe Arrays", (.ps), (.pdf), (.ppt), Proc. Intl. Conf. on Research in Computational Molecular Biology, apm:299oxAsrybEcM April 2003, pp. 148-156.
  159. S. V. Babin, A. B. Kahng, I. I. Mandoiu, and S. Muddu, "Resist Heating Dependence on Subfield Scheduling in 50kV Electron Beam Maskmaking", (.ps), (.pdf), (.ppt), Photomask and Next-Generation Lithography Mask Technology X, Proc. SPIE #5130, April 2003, pp. 718-726.
  160. Y. Chen, P. Gupta and A. B. Kahng, "Performance-Impact Limited Area Fill Synthesis", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 2003, pp. 22-27.
  161. P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, "A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 2003, pp. 16-21.
  162. H. Chen, C.-K. Cheng, N.-C. Chou, A. B. Kahng, J. F. MacDonald, P. Suaris, B. Yao and Z. Zhu, "An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 2003, pp. 794-799.
  163. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, "Design Flow Enhancements for DNA Arrays", (.ps), (.pdf), (.ppt), Proc. IEEE Intl. Conf. on Computer Design, October 2003, pp. 116-123.
  164. P. Gupta, A. B. Kahng, I. I. Mandoiu, and P. Sharma, "Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2003, pp. 754-759.
  165. A. B. Kahng, I. I. Mandoiu, S. Reda, X. Xu, and A. Zelikovsky, "Evaluation of Placement Techniques for DNA Probe Array Layout", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2003, pp. 262-269.
  166. H. Chen, C. K. Cheng, A. B. Kahng, I. I. Mandoiu, Q. Wang, and B. Yao, "The Y-Architecture for On-Chip Interconnect: Analysis and Methodology", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2003, pp. 13-19.
  167. P. Gupta and A. B. Kahng, "Manufacturing-Aware Physical Design", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM Intl. Conference on Computer-Aided Design, November 2003, (embedded tutorial) pp. 681-687.
  168. P. Gupta and A. B. Kahng, "Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling", (.ps), (.pdf), (.ppt), Proc. IEEE Intl. Conf. on VLSI Design , Jan 2004, pp. 431-436.
  169. H. Chen, C. K. Cheng, A. B. Kahng, M. Mori and Q. Wang, "Optimal Planning for Mesh-Based Power Distribution", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2004, pp. 444-449.
  170. A. B. Kahng and S. Reda, "Combinatorial Group Testing Methods for the BIST Diagnosis Problem", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2004, pp. 113-116.
  171. P. Gupta, A.B. Kahng, Y. Kim, and D. Sylvester, "Investigation of Performance Metrics for Interconnect Stack Architectures", (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, Feb. 2004, pp. 23-29.
  172. A. B. Kahng, I. Markov and S. Reda, "Boosting: Min-Cut Placement with Improved Signal Delay", (.ps), (.pdf), (.ppt), Proc. Design, Automation and Test in Europe, Feb. 2004, pp. 1098-1103.
  173. A. B. Kahng, I. I. Mandoiu, Q. Wang, X. Xu, and A. Zelikovsky, "MultiProject Reticle Floorplanning and Wafer Dicing", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2004, pp. 70-77.
  174. A. B. Kahng, and Q. Wang, "Implementation and Extensibility of an Analytic Placer", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2004, pp. 18-25.
  175. A. B. Kahng, I. L. Markov and S. Reda, "On Legalization of Row-Based Placements", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE GLSVLSI, April 2004, pp. 214-219.
  176. A. B. Kahng and S. Reda, "Placement Feedback: A Concept and Method for Better Min-Cut Placements", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 2004, pp.357-362.
  177. P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, "Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 2004, pp. 327-330.
  178. D. A. Antonelli, D. Z. Chen, T. J. Dysart, X. S. Hu, A. B. Kahng, P. M. Kogge, R. C. Murphy and M. T. Niemier, "Quantum-Dot Cellular Automata (QCA) Circuit Partitioning: Problem Modeling and Solutions", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 2004, pp. 363-368.
  179. L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester and J. Yang, "Toward a Methodology for Manufacturability-Driven Design Rule Exploration", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., June 2004, pp. 311-316.
  180. A. B. Kahng, X. Xu and A. Zelikovsky, "Yield- and Cost-Driven Fracturing for Variable Shaped-Beam Mask Writing", (.ps), (.pdf), (.ppt), Proc. 24th BACUS Symposium on Photomask Technology and Management, September 2004, pp. 360-371.
  181. P. Gupta, A. B. Kahng, C.-H. Park, P. Sharma, D. Sylvester and J. Yang, "Joining the Design and Mask Flows for Better and Cheaper Masks", (.ps), (.pdf), (.ppt), Proc. 24th BACUS Symposium on Photomask Technology and Management, 5567, 318 (2004).
  182. L. He, A. B. Kahng, K. H. Tam and J. Xiong, "Variability-Driven Considerations in the Design of Integrated-Circuit Global Interconnects", (.ps), (.pdf), (.ppt), Proc. 21st Intl. VLSI Multilevel Interconnection (VMIC) Conf., September 2004, pp. 214-221.
  183. A. B. Kahng, and S. Reda, "Reticle Floorplanning With Guaranteed Yield for Multi-Project Wafers", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer Design, October 2004, pp. 106-110.
  184. A. B. Kahng, and Q. Wang, "An Analytic Placer for Mixed-Size Placement and Timing-Driven Placement", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2004, pp. 565-572.
  185. Y. Chen, A. B. Kahng, G. Robins, A. Zelikovsky, and Y. Zheng, "Evaluation of the New OASIS Format for Layout Fill Compression", (.ps), (.pdf), (.ppt), Proc. 11th IEEE Intl. Conf. on Electronics, Circuits and Systems, December 2004, pp. 377-382.
  186. P. Gupta, A. B. Kahng and C.-H. Park, "Detailed Placement for Improved Depth of Focus and CD Control", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., Jan. 2005, pp. 343-348.
  187. P. Gupta, A. B. Kahng and C.-H. Park, "Manufacturing-Aware Design Methodology for Assist Feature Correctness", (.ps), (.pdf), (.ppt), Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, Feb. 2005, pp. 131-140.
  188. C. Chiang, A. B. Kahng, S. Sinha, X. Xu, and A. Zelikovsky, "Bright-field AAPSM Conflict Detection and Correction", (.ps), (.pdf), (.ppt), Proc. Design, Automation and Test in Europe, March 2005, pp. 908-913.
  189. P. Gupta, A. B. Kahng and P. Sharma, "A Practical Transistor-Level Threshold Voltage Assignment Methodology", (.ps), (.pdf), (.ppt), Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp. 261-265.
  190. P. Gupta, A.B. Kahng, D. Sylvester and J. Yang, "Performance-Driven OPC for Mask Cost Reduction", (.ps), (.pdf), (.ppt), Proc. IEEE International Symposium on Quality Electronic Design, March 2005, pp. 270-275.
  191. L. He, A. B. Kahng, K. Tam and J. Xiong, "Design of IC Interconnects with Accurate Modeling of CMP", (.ps), (.pdf), (.ppt), Proc. International Society for Optical Engineering (SPIE) Symposium on Microlithography, 5756, 109 (2005).
  192. A. B. Kahng and S. Reda, "Evaluation of Placer Suboptimality Via Zero-Change Netlist Transformations", (.ps), (.pdf), (.ppt), Proc. International Symposium on Physical Design, April 2005, pp 208-215.
  193. C. J. Alpert, A. B. Kahng, G-J. Nam, S. Reda and P. Villarrubia, "A Semi-Persistent Clustering Technique for VLSI Circuit Placement", (.ps), (.pdf), (.ppt), Proc. International Symposium on Physical Design, April 2005, pp. 200-207.
  194. L. He, A. B. Kahng, K. Tam and J. Xiong, "Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation", (.ps), (.pdf), (.ppt), Proc. International Symposium on Physical Design, April 2005, pp. 78-85.
  195. A. B. Kahng, S. Reda and Q. Wang, "APlace: A General Analytic Placement Framework", (.ps), (.pdf), (.ppt), Proc. International Symposium on Physical Design, April 2005, pp. 233-235.
  196. P. Gupta, A. B. Kahng, C.-H. Park, Kambiz Samadi and Xu Xu, "Wafer Topography-Aware Optical Proximity Correction for Better DOF Margin and CD Control", (.ps), (.pdf), (.ppt), Proc. Photomask and Next-Generation Lithography Mask Technology X, April 2005, pp. 844-854.
  197. P. Gupta, A. B. Kahng and C.-H. Park, "Improving OPC Quality Via Interactions Within the Design-to-Manufacturing Flow", (.ps), (.pdf), (.ppt), Proc. Photomask and Next-Generation Lithography Mask Technology X, April 2005, pp. 131-140.
  198. Y.-S. Cheon, P.-H. Ho, A. B. Kahng, S. Reda and Q. Wang, "Power-Aware Placement", (.ps), (.pdf), (.ppt), Proc. Design Automation Conference, June 2005, pp. 795-800.
  199. P. Gupta, A. B. Kahng, Y. Kim, and D. Sylvester, "Self-Compensating Design for Focus Variation", (.ps), (.pdf), (.ppt), Proc. Design Automation Conference, June 1995, pp. 365-368.
  200. A. B. Kahng, S. Muddu and P. Sharma, "Defocus-Aware Leakage Estimation and Control", (.ps), (.pdf), (.ppt), Proc. International Symposium on Low Power Electronics and Design, August 2005, pp. 263-268.
  201. P. Gupta, A. B. Kahng and C.-H. Park, "Enhanced Resist and Etch CD Control by Design Perturbation", (.ps), (.pdf), (.ppt), Proc. 25th BACUS Symposium on Photomask Technology and Management, 5992, 59923P (2005).
  202. P. Gupta, A. B. Kahng, S. Muddu, S. Nakagawa and C.-H. Park, "Modeling OPC Complexity for Design for Manufacturability", (.ps), (.pdf), (.ppt), Proc. 25th BACUS Symposium on Photomask Technology and Management, 5992, 59921W (2005).
  203. A. B. Kahng, I. I. Mandoiu, X. Xu, and A. Zelikovsky, "Yield-Driven Multi-Project Reticle Design and Wafer Dicing", (.ps), (.pdf), (.ppt), Proc. 25th BACUS Symposium on Photomask Technology and Management, 5992, 599249 (2005). (1st place in Best Poster Awards and Best Paper Award) (also appears in BACUS News March 2006, 22(3), pp. 1-10.)
  204. A. B. Kahng, B. Liu and Q. Wang, "Supply Voltage Degradation Aware Analytical Placement", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer Design, October 2005, pp. 437-443. (Best Paper award; 5 awards out of 310 submissions)
  205. P. Gupta, A. B. Kahng, O.S. Nakagawa and K. Samadi, "Closing the Loop in Interconnect Analyses and Optimization: CMP Fill, Lithography and Timing", (.ps), (.pdf), (.ppt), Proc. 22nd Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., October 2005, pp. 352-363.
  206. A. B. Kahng and S. Reda, "Intrinsic Shortest Path Length: A New, Accurate A Priori Wirelength Estimator", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2005, pp. 173-180.
  207. C. Chiang, A. B. Kahng, S. Sinha and X. Xu, "Fast and Efficient Phase Conflict Detection and Correction in Standard-Cell Layouts", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2005, pp. 149-156.
  208. A. B. Kahng, S. Reda and Q. Wang, "Architecture and Details of a High Quality, Large-Scale Analytical Placer", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2005, pp. 891-898. (Nominated for Best Paper award).
  209. P. Gupta and A.B. Kahng, "Efficient Design and Analysis of Robust Power Distribution Meshes", (.ps), (.pdf), (.ppt), Proc. International Conference on VLSI Design, Jan. 2006, pp. 337-342.
  210. A. B. Kahng, I. I. Mandoiu, X. Xu and A. Zelikovsky, "Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand", (.ps), (.pdf), (.ppt), Proc. European Mask and Lithography Conference, 6281, 628104 (2006). (Invited Paper).
  211. P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah and P. Sharma, "Lithography Simulation-Based Full-chip Design Analyses", (.ps), (.pdf), (.ppt), Proc. SPIE Conference on Design and Process Integration for Microelectronic Manufacturing, 6156, 61560T (2006).
  212. A. B. Kahng and R. O. Topaloglu, "Generation of Design Guarantees for Interconnect Matching", (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, March 2006, pp. 29-34.
  213. A. B. Kahng and S. Reda, "A Tale of Two Nets: Studies of Wirelength Progression in Physical Design", (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, March 2006, pp. 17-24.
  214. A. B. Kahng, B. Liu and X. Xu, "Statistical Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation", (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, March 2006, pp. 91-97.
  215. A. B. Kahng, C.-H. Park, P. Sharma and Q. Wang, "Lens Aberration Aware Timing-Driven Placement", (.ps), (.pdf), (.ppt), Proc. Design, Automation and Test in Europe, March 2006, pp. 890-895.
  216. A. B. Kahng, K. Samadi and P. Sharma, "Study of Floating Fill Impact on Interconnect Capacitance", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, April 2006, pp. 691-696.
  217. A. B. Kahng, B. Liu and X. Xu, "Constructing Current-Based Gate Models Based on Existing Timing Library", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, April 2006, pp. 37-42.
  218. A. B. Kahng, B. Liu and S. Tan, "SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, April 2006, pp. 638-643.
  219. A. B. Kahng, S. Muddu and P. Sharma, "Impact of Gate-Length Biasing on Threshold-Voltage Selection", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, April 2006, pp. 747-754.
  220. A. B. Kahng, B. Liu and S. Tan, "Efficient Decoupling Capacitor Planning via Convex Programming Methods", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Symp. on Physical Design, April 2006, pp. 102-107.
  221. A. B. Kahng and Q. Wang, "A Faster Implementation of APlace", (.ps), (.pdf), Proc. ACM/IEEE Intl. Symp. Physical Design, 2006, pp. 218-220. (Short Invited)
  222. A. B. Kahng, X. Xu and A. Zelikovsky, "Fast Yield-Driven Fracture for Variable Shaped-Beam Mask Writing", (.ps), (.pdf), (.ppt), Photomask and Next-Generation Lithography Mask Technology XI, Proc. SPIE 6283, 62832R, April 2006.
  223. A. B. Kahng, B. Liu and X. Xu, "Statistical Gate Delay Calculation with Crosstalk Alignment Consideration", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE GLSVLSI, April 2006, pp. 223-228.
  224. C. J. Alpert, A. B. Kahng, C. N. Sze and Q. Wang, "Timing-Driven Steiner Trees are (Practically) Free", (.ps), (.pdf), (slides), Proc. ACM/IEEE Design Automation Conference, July 2006, pp. 389-392.
  225. A. B. Kahng and C.-H. Park, "Auxiliary Pattern for Cell-Based OPC", (.ps), (.pdf), (.ppt), Proc. 27th BACUS Symposium on Photomask Technology and Management, 6349, 63494S (2006).
  226. A. B. Kahng, C.-H. Park and X. Xu, "Fast Dual-Graph Based Hotspot Detection", (.ps), (.pdf), (.ppt), Proc. 27th BACUS Symposium on Photomask Technology and Management, 6281, 628104 (2006).
  227. A. B. Kahng and X. Xu, "A General Framework for Multi-Flow, Multi-Layer, Multi-Project Reticles Design", (.ps), (.pdf), (.ppt), Proc. 27th BACUS Symposium on Photomask Technology and Management, 6349, 63494A (2006).
  228. A. Balasinski, J. Cetin, A. B. Kahng and X. Xu, "A Procedure and Program to Calculate Shuttle Mask Advantage", (.ps), (.pdf), (.ppt), Proc. 27th BACUS Symposium on Photomask Technology and Management, 6349, 63492B (2006).
  229. A. B. Kahng and R. O. Topaloglu, "Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction", (.ps), (.pdf), (.ppt), Proc. International Conference of Computer Design, October 2006, pp. 222-229.
  230. A. B. Kahng, P. Sharma, and A. Zelikovsky, "Fill for Shallow Trench Isolation CMP", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668. 
  231. J. Hu, A. B. Kahng, B. Liu, G. Venkataraman and X. Xu, "A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., January 2007, pp. 24-31.
  232. A. B. Kahng and R. O. Topaloglu, "A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, March 2007, pp. 467-474. (Best Paper award).
  233. A. B. Kahng, S. Reda and P. Sharma, "On-Line Adjustable Buffering for Runtime Power Reduction", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, March 2007, pp. 550-555. 
  234. A. B. Kahng, S. Muddu and P. Sharma, "Detailed Placement for Leakage Reduction using Systematic Through-Pitch Variation", (.ps), (.pdf), (.ppt), Proc. International Symposium on Low Power Electronics and Design, 2007, pp. 110-115. 
  235. A. B. Kahng, "Key Directions and a Roadmap for Electrical Design for Manufacturability", (.ps), (.pdf), (.ppt), Proc. European Solid-State Circuits Conf., 2007, pp. 83-88.  (Invited Paper).
  236. A. B. Kahng and R. O. Topaloglu, "Performance-Aware CMP Fill Pattern Optimization", (.ps), (.pdf), (.ppt), Proc. Intl. VLSI/ULSI Multilevel Interconnection (VMIC) Conf., 2007, pp. 135-144.  (Invited Paper).
  237. A. B. Kahng, S-.M Kang, W. Li and B. Liu, "Analytical Thermal Placement for VLSI Lifetime Improvement and Minimum Performance Variation", (.ps), (.pdf), (.ppt), Proc. International Conference of Computer Design, 2007, pp. 71-77. 
  238. A. B. Kahng, "Opportunities in Future Physical Implementation and Manufacturing Handoff Flows", (.ps), (.pdf), (.ppt), Proc. International SoC Design Conf., 2007, pp. 46-50.  (Invited Paper).
  239. A. B. Kahng, P. Sharma and R. O. Topaloglu, "Exploiting STI Stress for Performance", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2007, pp. 83-90. 
  240. P. Gupta, A. B. Kahng, Y. Kim, S. Shah, D. Sylvester, "Investigation of Diffusion Rounding for Post-Lithography Analysis", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., 2008, pp. 480-485 . 
  241. L. Carloni, A. B. Kahng, S. Muddu, A. Pinto, K. Samadi and P. Sharma, "Interconnect Modeling for Improved System-Level Design Optimization", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., 2008, pp. 258-264. 
  242. K. Jeong, A. B. Kahng and K. Samadi, "Quantified Impacts of Guardband Reduction on Design Process Outcomes", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, 2008, pp. 790-897. 
  243. P. Gupta, K. Jeong, A. B. Kahng and C.-H. Park, "Electrical Metrics for Lithographic Line-End Tapering", (.ps), (.pdf), (.ppt), Proc. Photomask and Next-Generation Lithography Mask Technology, 2008, pp. 70238A-1 - 70238A-12. 
  244. A. B. Kahng and S. Muddu, "Predictive Modeling of Lithography-Induced Linewidth Variation", (.ps), (.pdf), (.ppt), Proc. Photomask and Next-Generation Lithography Mask Technology, 2008, pp. 70280M-1 - 70280M-14 
  245. K. Jeong, A. B. Kahng, C.-H. Park and H. Yao, "Dose Map and Placement Co-Optimization for Timing Yield Enhancement and Leakage Power Reduction", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conference, 2008, pp. 516-521.
  246. P. Gupta and A. B. Kahng, "Bounded Lifetime Integrated Circuits", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conference, 2008, pp. 347-348.
  247. R. J. Greenway, K. Jeong, A. B. Kahng, C.-H. Park and J. S. Petersen, "32nm 1-D Regular Pitch SRAM Bitcell Design for Interference-Assisted Lithography", (.ps), (.pdf), (.ppt), Proc. SPIE BACUS Symposium on Photomask Technology and Management, 2008 7122, 71221L.
  248. A. B. Kahng, C.-H. Park, X. Xu and H. Yao, "Revisiting the Layout Decomposition Problem for Double Patterning Lithography", (.ps), (.pdf), (.ppt), Proc. SPIE BACUS Symposium on Photomask Technology and Management, 2008 7122, 712221
  249. A. B. Kahng, "Lithography and Design in Partnership: A New Roadmap", (.ps), (.pdf), (.ppt), Proc. SPIE BACUS Symposium on Photomask Technology and Management, 2008 7122, 712202.
  250. A. B. Kahng, C.-H. Park, X. Xu and H. Yao, "Layout Decomposition for Double Patterning Lithography", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2008, pp. 465-472. (nominated for Best Paper award)
  251. A. B. Kahng, K. Samadi and R. O. Topaloglu, "Recent Topics in CMP-Related IC Design for Manufacturing", (.ps), (.pdf), (.ppt), Proc. Materials Research Society, 2008.
  252. K. Jeong, A. B. Kahng and H. Yao, "On Modeling and Sensitivity of Via Count in SOC Physical Implementation", (.ps), (.pdf), (.ppt), Proc. International SoC Design Conf., 2008, pp. 125-128.  (Invited Paper).
  253. A. B. Kahng and K. Samadi, "Communication Modeling for System-Level Design", (.ps), (.pdf), (.ppt), Proc. International SoC Design Conf., 2008, pp. 138-143.  (Invited Paper).
  254. K. Jeong and A. B. Kahng, "Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., 2009, pp. 486-491.
  255. K. Jeong, A. B. Kahng and H. Yao, "Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, 2009, pp. 127-134.
  256. R. T. Greenway, R. Hendel, K. Jeong, A. B. Kahng, J. S. Petersen, Z. Rao and M. Smayling, "Interference Assisted Lithography for Patterning of 1D Gridded Design", (.ps), (.pdf), (.ppt), Proc. SPIE Symposium on Advanced Lithography, 2009 7271, 72712U.
  257. A. B. Kahng, B. Li, L.-S. Peh and K. Samadi, "ORION 2.0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration", (.ps), (.pdf), (.ppt), Proc. Design, Automation and Test in Europe, 2009, pp. 423-428.
  258. K. Jeong, A. B. Kahng and R. O. Topaloglu, "Is Overlay Error More Important Than Interconnect Variations in Double Patterning?" (.ps), (.pdf), (.ppt), Proc. ACM International Workshop on System-Level Interconnect Prediction, 2009, pp. 3-10.
  259. A. Coskun, A. B. Kahng and T. S. Rosing, "Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures", (.ps), (.pdf), (.ppt), Proc. Euromicro DSD, 2009, pp. 183-190.
  260. M. Gupta, K. Jeong and A. B. Kahng, "Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Double Patterning Lithography" (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2009, pp. 607-614.
  261. K. Jeong and A. B. Kahng, "A Power-Constrained MPU Roadmap for the International Technology Roadmap for Semiconductors (ITRS)", (.ps), (.pdf), (.ppt), Proc. International SoC Design Conf., 2009, pp. 49-52. (Invited Paper).
  262. K. Jeong, A. B. Kahng and K. Samadi, "Architectural-Level Prediction of Interconnect Wirelength and Fanout", (.ps), (.pdf), (.ppt), Proc. International SoC Design Conf., 2009, pp. 53-56. (Invited Paper).
  263. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "Slack Redistribution for Graceful Degradation Under Voltage Overscaling", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., 2010, pp. 825-831.
  264. A. B. Kahng, B. Lin and K. Samadi, "Improved On-Chip Router Analytical Power and Area Modeling", (.ps), (.pdf), (.ppt), Proc. Asia and South Pacific Design Automation Conf., 2010, pp. 241-246.
  265. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "Designing a Processor From the Ground Up to Allow Voltage/Reliability Tradeoffs", (.ps), (.pdf), (.ppt), Proc. International Symposium on High-Performance Computer Architecture, 2010, pp. 119-129.
  266. K. Jeong, A. B. Kahng and R. O. Topaloglu, "Assessing Chip-Level Impact of Double-Patterning Lithography", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, 2010, pp. 122-130.
  267. K. Jeong and A. B. Kahng, "Methodology From Chaos in IC Implementation", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, 2010, pp. 885-892.
  268. K. Jeong, A. B. Kahng and S. Kang, "Toward Effective Utilization of Timing Exceptions in Design Optimization", (.ps), (.pdf), (.ppt), Proc. International Symposium on Quality Electronic Design, 2010, pp. 54-61.
  269. C.-K. Cheng, A. B. Kahng, K. Samadi and A. Shayan, "Worst-Case Performance Prediction Under Supply Voltage and Temperature Variation", (.ps), (.pdf), (.ppt), Proc. System-Level Interconnect Prediction, 2010, pp. 91-96.
  270. A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "Recovery-Driven Design: A Power Minimization Methodology for Error-Tolerant Processor Modules", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conference, 2010, pp. 825-830.
  271. P. Gupta, A. B. Kahng, A. Kasibhatla and P. Sharma, "Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conference, 2010, pp. 597-602.
  272. A. B. Kahng, B. Lin, K. Samadi and R. S Ramanujam, "Trace-Driven Optimization of Networks-on-Chip Configurations", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conference, 2010, pp. 437-442.
  273. A. B. Kahng, B. Lin, K. Samadi and R. S Ramanujam, "Efficient Trace-Driven Metaheuristics for Optimization of Networks-on-Chip Configurations", (.ps), (.pdf), (.ppt), Proc. IEEE/ACM International Conference on Computer-Aided Design, 2010, pp. 253-263.
  274. C.-K. Cheng, P. Du, A. B. Kahng, G. K. H. Pang, Y. Wang and N. Wong, "More Realistic Power Grid Verification Based on Hierarchical Current and Power Constraints", (.ps), (.pdf), (.ppt), Proc. ACM Symp. on Physical Design., 2011, pp. 159-166.
  275. K. Jeong, A. B. Kahng and C. J. Progler, "New Yield-Aware Mask Strategies", (.ps), (.pdf), (.ppt), Proc. Photomask and Next-Generation Lithography Mask Technology, 2011, pp. 80810P-1--80810P-12.
  276. K. Jeong and A. B. Kahng, "Toward PDN Resource Estimation: A Law of Power Density", (.ps), (.pdf), (.ppt), Proc. System-Level Interconnect Prediction, 2011, pp. 1-6.
  277. S. K. Han, K. Jeong, A. B. Kahng and J. Lu, "Stability and Scalability in Global Routing", (.ps), (.pdf), (.ppt), Proc. System-Level Interconnect Prediction, 2011, pp. 1-6.
  278. A. B. Kahng and V. Srinivas, "Mobile System Considerations for SDRAM Interface Trends", (.ps), (.pdf), (.ppt), Proc. System-Level Interconnect Prediction, 2011, pp. 1-8.
  279. T.-B. Chan, K. Jeong and A. B. Kahng, "Performance and Variability Driven Guidelines for BEOL Layout Decomposition with LELE Double Patterning", (.ps), (.pdf), (.ppt), Proc. SPIE BACUS Symposium on Photomask Technology, 2011, 8166, 81663O-1-81663O-12.
  280. K. Jeong, A. B. Kahng, S. Kang, T. S. Rosing and R. Strong, "MAPG: Memory Access Power Gating", (.ps), (.pdf), (.ppt), Proc. Design, Automation and Test in Europe, 2012, pp. 1054-1059.
  281. T.-B. Chan, P. Gupta, A. B. Kahng and L. Lai, "DDRO: A Novel Performance Monitoring Methodology Based on Design-Dependent Ring Oscillators", (.ps), (.pdf), (.ppt), Proc. Intl. Symposium on Quality Electronic Design, 2012, pp. 633-640.
  282. T.-B. Chan and A. B. Kahng, "Improved Path Clustering for Adaptive Path-Delay Testing", (.ps), (.pdf), (.ppt), Proc. Intl. Symposium on Quality Electronic Design, 2012, pp. 13-20.
  283. C. K. Cheng, P. Du, A. B. Kahng and S. Weng, "Low-Power Gated Bus Synthesis for 3D IC via Rectilinear Shortest-path Steiner Graph", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Symp. Physical Design, 2012, pp. 105-112.
  284. A. B. Kahng and S. Kang, "Construction of Realistic Gate Sizing Benchmarks With Known Optimal Solutions", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Intl. Symp. Physical Design, 2012, pp. 153-160.
  285. A. B. Kahng, B. Lin and S. Nath, "Explicit Modeling of Control and Data for Improved NoC Router Estimation", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., 2012, pp. 392-397 (nominated for Best Paper Award; 7 nominees out of 744 submissions). 
  286. A. B. Kahng and S. Kang, "Accuracy-Configurable Adder for Approximate Arithmetic Designs", (.ps), (.pdf), (.ppt), Proc. ACM/IEEE Design Automation Conf., 2012, pp. 820-825. 
  287. A. B. Kahng, S. Kang, T. S. Rosing and R. Strong, "TAP - Token-Based Adaptive Power Gating", (.ps), (.pdf), (.ppt), Proc. International Symposium on Low Power Electronics and Design, 2012, pp. 203-208. 
  288. J. Hu, A. B. Kahng, S. Kang, M. Kim and I. Markov, "Sensitivity-guided Metaheuristics for Accurate Discrete Gate Sizing", (.pdf), (.pptx), Proc. IEEE/ACM International Conference on Computer-Aided Design, 2012, pp. 233-239.
  289. T.-B. Chan and A. B. Kahng, "Tunable Sensors for Process-Aware Voltage Scaling", (.pdf), (.pptx), Proc. IEEE/ACM International Conference on Computer-Aided Design, 2012, pp. 7-14.
  290. N. Jouppi, A. B. Kahng, N. Muralimanohar and V. Srinivas, "CACTI-IO: CACTI with Off-chip Power-Area-Timing Models", (.pdf), (.pptx), Proc. IEEE/ACM International Conference on Computer-Aided Design, 2012, pp. 294-301.
  291. T.-B. Chan, A. B. Kahng, J. Li and S. Nath, "Optimization of Overdrive Signoff", (.pdf), (.pptx), Proc. Asia and South Pacific Design Automation Conf., 2013, pp. 344 - 349.
  292. A. B. Kahng, S. Nath and T. S. Rosing, "On Potential Design Impacts of Electromigration Awareness", (.pdf), (.pptx), Proc. Asia and South Pacific Design Automation Conf., 2013, pp. 527-532.
  293. T.-B. Chan and A. B. Kahng, "Post-Routing Back-End-of-Line Layout Optimization for Improved Time-Dependent Dielectric Breakdown Reliability", (.pdf), (.pptx), Proc. SPIE Symposium on Advanced Lithography, 2013 8684, 86840L.
  294. T.-B. Chan, W.-T. J. Chan and A. B. Kahng, "Impact of Adaptive Voltage Scaling on Aging-Aware Signoff", (.pdf), (.pptx), Proc. Design, Automation and Test in Europe, 2013, pp. 1683-1688.
  295. A. B. Kahng, S. Kang and B. Park, "Active-Mode Leakage Reduction with Data-Retained Power Gating", (.pdf), (.pptx), Proc. Design, Automation and Test in Europe, 2013, pp. 1209-1214.
  296. A. B. Kahng, B. Lin and S. Nath, "Enhanced Metamodeling Techniques for High-Dimensional IC Design Estimation Problems", (.pdf), (.pptx), Proc. Design, Automation and Test in Europe, 2013, pp. 1861-1866.
  297. T.-B. Chan, A. B. Kahng and J. Li, "Reliability-Constrained Die Stacking Order in 3DICs under Manufacturing Variability", (.pdf), (.pptx), Proc. International Symposium on Quality in Electronic Design , 2013, pp. 16-23.
  298. T.-B. Chan, A. B. Kahng and J. Li, "Toward Quantifying the IC Design Value of Interconnect Technology Improvements", (.pdf), (.pptx), Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, 2013.
  299. A. B. Kahng, S. Kang, H. Lee, S. Nath and J. Wadhwani, "Learning-Based Approximation of Interconnect Delay and Slew in Signoff Timing Tools", (.pdf), (.pptx), Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, 2013.
  300. A. B. Kahng, B. Lin and S. Nath, "High-Dimensional Metamodeling for Prediction of Clock Tree Synthesis Outcomes", (.pdf), (.pptx), Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, 2013.
  301. A. B. Kahng, S. Kang and H. Lee, "Smart Non-Default Routing for Clock Power Reduction", (.pdf), (.pptx), Proc. ACM/IEEE Design Automation Conf., 2013.
  302. A. B. Kahng, "The ITRS Design Technology and System Drivers Roadmap: Process and Status", (.pdf), Proc. ACM/IEEE Design Automation Conf., 2013. (Invited Paper)
  303. W.-T. J. Chan, A. B. Kahng, S. Kang, R. Kumar and J. Sartori, "Statistical Analysis and Modeling for Error Composition in Approximate Computation Circuits", (.pdf), (.pptx), Proc. IEEE Intl. Conf. on Computer Design, 2013, pp. 47-53.
  304. A. B. Kahng, S. Kang, H. Lee, I. L. Markov and P. Thapar, "High-Performance Gate Sizing with a Signoff Timer", (.pdf), (.pptx), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2013, pp. 450-457.
  305. A. B. Kahng, I. Kang and S. Nath, "Incremental Multiple-Scan Chain Ordering for ECO Flip-Flop Insertion", (.pdf), (.pptx), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2013, pp. 705-712.
  306. A. B. Kahng, "Lithography-Induced Limits to Scaling of Design Quality", (.pdf), Proc. Design-Process-Technology Co-optimization for Manufacturability VIII (SPIE Microlithography Symposium), 2014, pp. 905302-1-905302-14. (Invited Paper)
  307. T.-B. Chan, A. B. Kahng and J. Li, "NOLO: A No-Loop, Predictive Useful Skew Methodology for Improved Timing in IC Implementation", (.pdf), (.pptx), Proc. International Symposium on Quality in Electronic Design, 2014, pp. 504-509.
  308. A. B. Kahng and H. Lee, "Margin Recovery with Flexible Flip-Flop Timing", (.pdf), (.pptx), Proc. International Symposium on Quality Electronic Design, 2014, pp. 496-503.
  309. A. B. Kahng and S. Nath, "Optimal Reliability-Constrained Overdrive Frequency Selection in Multicore Systems", (.pdf), (.pptx), Proc. International Symposium on Quality Electronic Design, 2014, pp. 300-308.
  310. A. B. Kahng and I. Kang, "Co-Optimization of Memory BIST Grouping, Test Scheduling, and Logic Placement", (.pdf), (.pptx), Proc. Design, Automation and Test in Europe, 2014, pp. 196:1-196:6.
  311. S. S. Han, A. B. Kahng, S. Nath and A. Vydyanathan, "A Deep Learning Methodology to Proliferate Golden Signoff Timing", (.pdf), (.pptx), Proc. Design, Automation and Test in Europe, 2014.
  312. G. Jerke and A. B. Kahng, "Mission Profile Aware IC Design -- A Case Study", (.pdf), (.pptx), Proc. Design Automation and Test in Europe, 2014.
  313. A. B. Kahng, H. Lee and J. Li, "Horizontal Benchmark Extension for Improved Assessment of Physical CAD Research", (.pdf), (.pptx), Proc. Great Lakes Symposium on VLSI, 2014, pp. 27-32.
  314. A. B. Kahng, S. Kang and J. Li, "A New Methodology for Reduced Cost of Resilience", (.pdf), (.pptx), Proc. Great Lakes Symposium on VLSI, 2014, pp. 157-162.
  315. A. B. Kahng and H. Lee, "Minimum Implant Area-Aware Gate Sizing and Placement", (.pdf), (.pptx), Proc. Great Lakes Symposium on VLSI, 2014, pp. 57-62. (nominated for Best Paper award)
  316. T.-B. Chan, K. Han, A. B. Kahng, J.-G. Lee and S. Nath, "OCV-Aware Top-Level Clock Tree Optimization", (.pdf), (.pptx), Proc. Great Lakes Symposium on VLSI, 2014, pp. 33-38.
  317. W.-T. J. Chan, A. B. Kahng and S. Nath, "Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling", (.pdf), (.pptx), Proc. Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, 2014, pp. 1-7.
  318. A. B. Kahng, "Toward Holistic Modeling, Margining and Tolerance of IC Variability", (.pdf), (.pptx), Proc. ISVLSI, July 2014, pp. 284-289. (Invited Paper)
  319. J.-A. Carballo, W.-T. J. Chan, P. A. Gargini, A. B. Kahng and S. Nath, "ITRS 2.0: Toward a Re-Framing of the Semiconductor Technology Roadmap", (.pdf), Proc. IEEE Intl. Conf. on Computer Design, 2014, pp. 139-146.
  320. W.-T. J. Chan, A. B. Kahng, S. Nath and I. Yamamoto, "The ITRS MPU and SOC System Drivers: Calibration and Implications for Design-Based Equivalent Scaling in the Roadmap", (.pdf), (.pptx), Proc. IEEE Intl. Conf. on Computer Design, 2014, pp. 153-160.
  321. T.-B. Chan, S. Dobre and A. B. Kahng, "Improved Signoff Methodology with Tightened BEOL Corners", (.pdf), Proc. IEEE Intl. Conf. on Computer Design, 2014, pp. 311-316.
  322. T.-B. Chan, P. Gupta, K. Han, A. A. Kagalwalla, A. B. Kahng and E. Sahouria, "Benchmarking of Mask Fracturing Heuristics", (.pdf), (.pptx), Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, 2014, pp. 246-253.
  323. Y. Chen, A. B. Kahng, B. Liu and W. Wang, "Crosstalk-Aware Signal Probability-Based Dynamic Statistical Timing Analysis", (.pdf), Proc. International Symposium on Quality in Electronic Design, 2015, pp. 424-429.
  324. S. Bang, K. Han, A. B. Kahng and V. Srinivas, "Clock Clustering and IO Optimization for 3D Integration", Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, (.pdf), (.pptx), 2015.
  325. A. B. Kahng, M. Luo and S. Nath, "SI for Free: Machine Learning of Interconnect Coupling Delay and Transition Effects", (.pdf), (.pptx), Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, 2015.
  326. M. Escalante, A. B. Kahng, M. Kishinevsky, U. Ogras and K. Samadi, "Multi-Product Floorplan and Uncore Design Framework for Chip Multiprocessors", Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, (.pdf), (.pptx), 2015.
  327. K. Han, A. B. Kahng, J. Lee, J. Li and S. Nath, "A Global-Local Optimization Framework for Simultaneous Multi-Mode Multi-Corner Skew Variation Reduction", (.pdf), (.pptx), Proc. ACM/IEEE Design Automation Conf., 2015.
  328. K. Han, A. B. Kahng and H. Lee, "Evaluation of BEOL Design Rule Impacts Using an Optimal ILP-Based Detailed Router", (.pdf), (.pptx), Proc. ACM/IEEE Design Automation Conf., 2015.
  329. W.-T. J. Chan, Y. Du, A. B. Kahng, S. Nath and K. Samadi, "3D-IC Benefit Estimation and Implementation Guidance from 2D-IC Implementation", (.pdf), (.pptx), Proc. ACM/IEEE Design Automation Conf., 2015.
  330. A. B. Kahng, "New Game, New Goal Posts: A Recent History of Timing Closure", (.pdf), (.pptx), Proc. ACM/IEEE Design Automation Conf., 2015. (Invited Paper)
  331. K. Han, A. B. Kahng, H. Lee and L. Wang, "ILP-Based Co-Optimization of Cut-Mask Layout, Dummy Fill and Timing for Sub-14nm BEOL Technology", (.pdf), (.pptx), Proc. 36th BACUS Symposium on Photomask Technology and Management, 2015. (nominated for Best Paper award)
  332. K. Han, A. B. Kahng and H. Lee, "Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints", (.pdf), (.pptx), IEEE/ACM International Conference on Computer-Aided Design, 2015.
  333. A. Alaghi, W.-T. J. Chan, J. P. Hayes, A. B. Kahng and J. Li, "Optimizing Stochastic Circuits for Accuracy-Energy Tradeoffs", (.pdf), (.pptx), IEEE/ACM International Conference on Computer-Aided Design, 2015.
  334. S. Dobre, A. B. Kahng and J. Li, "Mixed Cell-Height Implementation for Improved Design Quality in Advanced Nodes", (.pdf), (.pptx), IEEE/ACM International Conference on Computer-Aided Design, 2015.
  335. A. B. Kahng and F. Koushanfar, "Evolving EDA Beyond its E-Roots: An Overview", (.pdf), (.pptx), IEEE/ACM International Conference on Computer-Aided Design, 2015, pp. 247-254. (Invited Paper)
  336. A. B. Kahng, M. Luo, G.-J. Nam, S. Nath, D. Z. Pan and G. Robins, "Toward Metrics of Design Automation Research Impact", (.pdf), (.pptx), IEEE/ACM International Conference on Computer-Aided Design, 2015, pp. 263-270. (Invited Paper)
  337. S. Bang, K. Han, A. B. Kahng and M. Luo, "Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products", (.pdf), (.pptx), Proc. Asia and South Pacific Design Automation Conf., 2016, pp. 697-704.
  338. W.-T. J. Chan, K. Y. Chung, A. B. Kahng, N. D. MacDonald and S. Nath, "Learning-Based Prediction of Embedded Memory Timing Failures During Initial Floorplan Design", (.pdf), (.pptx), Proc. Asia and South Pacific Design Automation Conf., 2016, pp. 178-185.
  339. A. Coskun, A. Gu, W. Jin, A. J. Joshi, A. B. Kahng, J. Klamkin, Y. Ma, J. Recchio, V. Srinivas and T. Zhang, "Cross-Layer Floorplan Optimization For Silicon Photonic NoCs In Many-Core Systems", Proc. Design, Automation and Test in Europe, 2016, pp. 1309-1314.
  340. K. Han, A. B. Kahng and J. Li, "Improved Performance of 3DIC Implementations Through Inherent Awareness of Mix-and-Match Die Stacking", (.pdf), (.pptx), Proc. Design, Automation and Test in Europe, 2016, pp. 61-66.
  341. W.-T. J. Chan, A. B. Kahng and J. Li, "Revisiting 3DIC Benefit with Multiple Tiers", (.pdf), Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, 2016, pp. 6:1-6:8.
  342. Kun Young Chung, A. B. Kahng and J. Li, "Comprehensive Optimization of Scan Chain Timing During Late-Stage IC Implementation", (.pdf), (.pptx), Proc. ACM/IEEE Design Automation Conf., 2016, pp. 61:1-61:6.
  343. A. B. Kahng, J. Li and L. Wang, "Improved Flop Tray-Based Design Implementation for Power Reduction", IEEE/ACM International Conference on Computer-Aided Design, 2016, to appear.