MARCO GSRC Calibrating Achievable Design: Bookshelf

Wirelength-driven Standard-cell Placement

(see other slots)

Work in progress: last updated Fri Jun 2, 2000
Andrew Caldwell Andrew B. Kahng Igor Markov

Contents

I. Introduction 
II. New Placement Formats
III.Publicly available instances, solutions and reference performance results
IV.Executable Utilities (converters, generators, statistics browsers, evaluators, constraint verifiers)
V.Optimizers and other non-trivial executables
VI.Common in-memory representations, parsers and other source codes


I. Introduction

VLSI placement is a major step in physical design of electronic circuits. It locates standard cells over the core region so as to minimize an objective function that represents a cumulative measure of delay and utilization. Placement with more detailed timing-related objectives will be considered in a different slot. Placement solutions must satisfy various combinatorial constraints, e.g., use only prescribed module locations, avoid module overlaps etc. This is what makes the problem difficult.

Proceedings of the Design Automation Conference for the last few years (relevant sections thereof) have a good coverage of approaches to VLSI placement, state-of-the-art and open research problems.

Standard-cell row-based placement and routing can be performed in two major ways: variable-die or fixed-die. Variable-die methodology dates back to 2-layer metal (2-LM) processes. Fixed-die methodology is the modern standard, and is appropriate to N-layer metal (N-LM) processes, N >= 3. Details of the two approaches are described in a separate document


II. New Placement Formats

The proposed formats have been designed according to general guidelines for data formats in the GSRC bookshelf, and are intended for standardization within the partitioning and placement slot, replacing or coexisting with previously available formats. This slot will provide benchmark instances in the new formats, including instanes earlier available in other formats, as well as a variety of executables and source code for conversion, evaluation and optimization.

Rev1.1 of new format descriptions.


III. Publicly available instances, solutions and reference performance results

"Dragon" benchmarks generated from ISPD-98/IBM netlists

The following netlists were generated from publically available hypergraph partitioning instances which were originally based on circuit netlists. Width and height for core cells were choosen such that their product is the node's original weight, and all core cells will have the same height. The layout files were generated with the AutoLayoutGenerator.

 A complete placement problem consists of the netlist files(nodes/nets/wts) and the layout files (scl/pl). An aux file is included with each layout collection.

 The netlist and layout statistics are available for each testcase, along with a list of reference placements. The current best-available placement is listed in the table. If you have competative placements you would like to make available we can post them here for you.

Note: these placements are the best known, even for the solver that produeced them. See the solver page for more detailed information. If you wish to compare the quality of produced placements to your implementation, it is better to download the executables and run them on the same benchmark files as your placer, on the same machine. It is highly recommended to discuss any such comparisons with authors to make sure that the command-line parameters are used correctly.

Netlist Files Layout Files Statistics and Reference Placements
IBM05 2% Whitespace, Aspect Ratio 1.0 Last Updated on Sept 21, 1999
10% Whitespace, Aspect Ratio 1.0 Last Updated on Sept 21, 1999
primary1-unitArea 2% Whitespace, Aspect Ratio 1.0 Last Updated on Sept 21, 1999
10% Whitespace, Aspect Ratio 1.0 Last Updated on Sept 21, 1999

MCNC Benchmarks in the new placement formats. The conversions from TW placements were provided by Professor Patrick Madden.

Note: since the layout area in 10% variants is bigger, wirelengths are not directly comparable.


IV. Executable Utilities (converters, generators, statistics browsers, evaluators, constraint verifiers)
AutoLayoutGenerator (Sun Solaris 2.7) (Intel Linux) (Win95/98/NT)
produces a layout (.scl and .pl for pads) having specified aspect-ratio and whitespace. Produces a rectangular layout with vertically abutting equal-length rows of alternating site orientations (i.e N, FS, N, FS...)
WireLengthCalculator (Sun Solaris 2.7) (Intel Linux) (Win95/98/NT)
computes center-to-center and pin-to-pin HalfPerimeter wirelength given .nodes/.nets/.wts/.scl/.pl files. May also be used to check that a set of placement files meets the standard.
LegalityChecker (Sun Solaris 2.7) (Intel Linux) (Win95/98/NT)
verifies that all core cells are placed at legal sites and are non-overlapping.

V. Optmizers and other non-trivial executables
VI. Common in-memory representations, parsers and other source codes

UCLA/UMich PD tools release


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 caldwell@cs.ucla.edu,abk@ucsd.edu,imarkov@cs.ucla.edu