UCSD VLSI CAD LABORATORY














Last Modified: October 11, 2006
  •  Minimizing Manufacturing Cost for Multi-Project Wafer (.ppt)
  •  Mask-writing Strategies for Increased CD Accuracy and Throughput (.ppt)
  •  Compressibility and Compression of VLSI Dummy Fill using the OASIS Format (.ppt)
  •  GTX: Status and Directions (.ppt)
  •  The GSRC METRICS Initiative (.ppt)
  •  Performance Impact-Limited Area Fill Synthesis for VLSI (.ppt)
  •  A Cost-Driven Lithographic Correction Methodology Based on Off-the-Shelf Sizing Tools (.ppt)
  •  The Y-Architecture for On-Chip Interconnect: Analysis and Methodology (.ppt)