Electrical and Computer Engineering Dept
University of California, San Diego
San Diego, CA 92093-0407

Phone: (858) 699-2983
Fax: (858) 534-5273
Email: smuddu@ucsd.edu
Office: 3819 APM, UCSD

Home page of Swamy Muddu

Areas of Interest

Design for Manufacturability, Characterization of Manufacturing Variation, CAD for Low Power and Computer Architecture

Biographical Sketch

Swamy Muddu received his Bachelor of Engineering in Electronics and Communication Engg from Osmania University, Hyderabad in 2001. He received his M.S. degree in Computer Engg. from UCSD in 2003 and is currently a candidate for Ph.D.

Research

Swamy's current research is on characterization and modeling of IC manufacturing variation. He is interested in technology aspects of IC physical design, electronic design process and technology roadmapping. He contributed to the 2003 International Technology Roadmap for Semiconductors

Though unconnected with VLSI and CAD, he maintains interest in renewable energy sources, clean energy and next-generation propulsion systems.

Selected Publications

(author names are ordered alphabetically in VLSICAD group)

• S.V. Babin, A.B. Kahng, I.I. Mandoiu, and S. Muddu, "Subfield scheduling for throughput maximization in electron-beam photomask fabrication", Emerging Lithographic Technologies VII, Proc. SPIE #5037, Feb. 2003, pp. 934-942


• P. Dasgupta, A.B. Kahng, and S. Muddu, "A Novel Metric for Interconnect Architecture Performance", Proc. Design Automation and Testing in Europe, March 2003, pp. 448-453


• S.V. Babin, A.B. Kahng, I.I. Mandoiu, and S. Muddu, "Resist Heating Dependence on Subfield Scheduling in 50kV Electron Beam Maskmaking", Photomask and Next-Generation Lithography Mask Technology X, Proc. SPIE #5130, April 2003, pp. 718-726


• S. Babin, A.B. Kahng, I.I. Mandoiu and S. Muddu, "Improving CD Accuracy and Throughput by Subfield Scheduling in Electron Beam Mask Writing", to appear in Journal of Vacuum Science and Technol. B.


• A.B. Kahng, S. Muddu and P. Sharma, "Defocus-aware leakage estimation and control", Proc. of the International Symposium on Low Power Electronics and Design, August 2005, pp. 263-268


• P. Gupta, A.B. Kahng and S. Muddu, "Quantifying Error in Dynamic Power Estimation of CMOS Circuits", Journal of Analog Integrated Circuits and Signal Processing, 42(3), 2005, pp. 253-264.


• P. Gupta, A.B. Kahng, S. Muddu, S. Nakagawa and C.-H. Park,"Modeling OPC Complexity for Design for Manufacturability", Proc. of 25th BACUS Symposium on Photomask Technology and Management, October 2005, to appear


• A.B. Kahng, S. Muddu and P. Sharma, "Impact of Gate-Length Biasing on Threshold-Voltage Selection", Proc. of International Symposium on Quality Electronic Design, April 2006, to appear


• P. Gupta, A.B. Kahng, S. Muddu, S. Nakagawa, "Modeling Edge Placement Error Distribution in Standard Cell Library", Design and Process Integration for Microelectronic Manufacturing IV, Proc. SPIE #6156, Feb. 2006, to appear