UCSD VLSI CAD LABORATORY














Last Modified: October 11, 2006

Puneet Sharma
Ph.D. Student
Electrical and Computer Engineering Dept
University of California, San Diego
San Diego, CA 92093-0407

Phone: (858) 822-5003
Fax: (858) 534-5273
Email: sharma@ucsd.edu
Office: 2144 EBU3B, UCSD

Homepage of Puneet Sharma



Areas of Interest

Design for Manufacturability, Process Variability, Power Analysis and Optimization

Biographical Sketch

Puneet Sharma received his Bachelor of Technology in Computer Science from Indian Institute of Technology, Delhi in 2002. He joined the Electrical Engineering Department at UCSD in September 2002.

Research

Puneet's past and ongoing research is in two of the most critical challenges faced by the semiconductor industry today - process variability and increasing leakage power. CMOS device scaling has outpaced advancements in manufacturing technology and consequently process variability, as a fraction of feature size, continues to increase. Impact of process variations on power and performance is further exacerbated by superlinear dependence of several electrical metrics on feature size (e.g., subthreshold leakage on gate length, gate tunneling leakage on gate-oxide thickness). Power, and especially leakage power, is another major challenge faced by the designers today. Supply voltage lowering to reduce dynamic power necessitates threshold voltage lowering to sustain high-performance and to allow for noise margins. Unfortunately, threshold voltage lowering causes a near-exponential increase in leakage power causing its share in total power to increase. Leakage variability and gate tunneling leakage are other important problems that need to be addressed for continued CMOS scaling.

Selected Publications

  • A. B. Kahng, P. Sharma, and A. Zelikovsky, "Fill for Shallow Trench Isolation CMP", Intl. Conf. on Computer-Aided Design, to appear, 2006 (ICCAD06).[PS] [PDF]
  • P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, "Gate-Length Biasing for Runtime Leakage Control", in IEEE Transactions on Computer-Aided Design, 2006, to appear (TCAD06).
  • A. B. Kahng, S. Muddu and P. Sharma, "Impact of Gate-Length Biasing on Threshold-Voltage Selection", Intl. Symp. on Quality Electronic Design, pp. 747- 754, 2006 (ISQED06). [PS] [PDF]
  • A. B. Kahng, K. Samadi and P. Sharma, "Study of Floating Fill Impact on Interconnect Capacitance", Intl. Symp. on Quality Electronic Design, pp. 691- 696, 2006 (ISQED06). [PS] [PDF]
  • A. B. Kahng, C.-H. Park, P. Sharma and Q. Wang, "Lens Aberration Aware Timing-Driven Placement", Proc. Design Automation and Testing in Europe, pp. 890-895, 2006 (DATE06). [PS] [PDF]
  • P. Gupta, A. B. Kahng, S. Nakagawa, S. Shah and P. Sharma, "Lithography Simulation-Based Full-Chip Design Analyses", in Proc. SPIE Conf. on Design and Process Integration for Microelectronic Manufacturing, pp. 61560T-1 -- 61560T-8, 2006 (SPIE06). [PS] [PDF]
  • P. Gupta, A. B. Kahng, I. I. Mandoiu and P. Sharma, "Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage", in IEEE Trans. on Computer-Aided Design, vol. 24, no. 7, pp. 1104-1114, 2005 (TCAD05). [PS] [PDF]
  • A. B. Kahng, S. Muddu and P. Sharma, "Defocus-Aware Leakage Estimation and Control", in Proc. Intl. Symp. on Low Power Electronics and Design, pp. 263 - 268, 2005 (ISLPED05). [PS] [PDF]
  • P. Gupta, A. B. Kahng, P. Sharma, "A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology", in Proc. IEEE Intl. Symp. on Quality Electronic Design, pp. 421-426, 2005 (ISQED05). [PS] [PDF]
  • P. Gupta, A. B. Kahng, C.-H. Park, P. Sharma, D. Sylvester and J. Yang, "Joining the Design and Mask Flows for Better and Cheaper Masks", INVITED in Proc. 24th BACUS Symp. on Photomask Technology and Management, pp. 318-329, 2004 (SPIE04). [PS] [PDF]
  • P. Gupta, A. B. Kahng, P. Sharma and D. Sylvester, "Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control", in ACM/IEEE Proc. of Design Automation Conf., pp. 327-330, 2004 (DAC04). [PS] [PDF]
  • P. Gupta, A. B. Kahng, I. Mandoiu and P. Sharma, "Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage", in IEEE Proc. of Intl. Conf. on Computer Aided Design, pp. 754-759, 2003 (ICCAD03). [PS] [PDF]