UCSD VLSI CAD LABORATORY
Last Modified: October 11, 2006
University of California, San Diego
CSE and ECE Departments
9500 Gilman Drive
La Jolla, CA 92093-0114
Work Phone: (858) 822-5003
Areas of InterestVLSI physical design automation: timing analysis and delay calculation, signal integrity analysis, yield and variation aware optimization, timing-driven interconnect synthesis.
Biographical SketchDr. Liu received his Ph.D. degree in Computer Science and Engineering from UCSD in 2003, and his B.S. and M.S. degrees in Electrical Engineering from Fudan University, China in 1993 and 1996, respectively. He worked with China IC Design Center in 1996-1998, Cadence Design Systems, Inc. in 1999, Conexant Systems, Inc. in 2000, Incentia Design Systems, Inc. in 2002-2004, and Cadence Design Systems, Inc. in 2004, respectively. He is currently a post-doctoral researcher with Professor Andrew Kahng in the Computer Science and Engineering Department, and a lecturer in the Electrical and Computer Engineering Department at UCSD.
ResearchDr. Liu's current research focuses on VLSI design performance verification, signal integrity analysis, and corresponding optimization techniques.