UCSD VLSI CAD LABORATORY
Last Modified: October 11, 2006
Andrew B. Kahng
Professor of CSE and ECE
Computer Science and Engineering Dept
Electrical and Computer Engineering Dept
University of California, San Diego
San Diego, CA 92093-0114
Phone: (858) 822-4884
Areas of InterestProfessor Kahng's research interests include algorithms and methodologies for the computer-aided physical design of VLSI circuits, performance analysis of circuits and interconnects, discrete algorithms, and combinatorial and large-scale heuristic optimization. Major research foci include (1) the semiconductor design-manufacturing interface, especially the cost-effective mitigation and compensation of manufacturing process variability, (2) semiconductor technology and system roadmapping, and (3) fundamental algorithms and optimizations for (module, interconnect) layout synthesis in digital and mixed-signal designs at all levels of system hierarchy. Professor Kahng's group also has interests in other applied algorithmics contexts such as networking, bioinformatics, and computational commerce.
Biographical SketchAndrew B. Kahng (b. Oct. 1963, San Diego, CA) received the A.B. degree in applied mathematics (physics) from Harvard College, and from June 1983 to June 1986 was affiliated with Burroughs Corporation Micro Components Group in San Diego, where he worked in device physics, circuit simulation, and CAD for VLSI layout. He received the M.S. and Ph.D. degrees in computer science from the University of California at San Diego. He joined the UCLA computer science department as an assistant professor in July 1989, and became associate professor in July 1994 and full professor (at age 34) in July 1998. From April 1996 through September 1997, he was on sabbatical leave and leave of absence from UCLA, as Visiting Scientist at Cadence Design Systems, Inc. He resumed his duties at UCLA in Fall 1997, and from July 1998 to September 2000 served as the computer science department's vice-chair for graduate studies. Effective January 1, 2001 Professor Kahng joined UCSD as Professor in the CSE and ECE Departments. He served as Associate Chair of the UCSD CSE Department from 2003-2004. In October 2004, Professor Kahng co-founded Blaze DFM, Inc., an EDA software company that delivered new cost and yield optimizations at the IC design-manufacturing interface. He served as CTO of the company during a two-year leave of absence, returning to the university full-time in September 2006. The Blaze DFM core technology is responsible for substantial leakage power and total power reductions in such high-volume products as AMD/ATI Radeon graphics processor chips, and is embodied today in the TSMC Power Trim Service that enables low integrated-circuit power consumption and green products.
Professor Kahng is the author of 3 books and well over 350 journal and conference papers. He holds 17 issued U. S. patents. His 22 Ph.D. graduates (Robins, Hagen, Boese, Alpert, Tsao, Muddu, Huang, Masuko, Markov, Liu, Chen, Mantik, Xu, Wang, Reda, Gupta, Sharma, Muddu, Park, Topaloglu, Samadi, Jeong) have gone on to notable successes in both academia and industry. He has received NSF Research Initiation and Young Investigator awards, 13 Best Paper nominations, and 6 Best Paper awards (DAC, ISQED (2), ICCD, ASP-DAC/VLSI Design, and BACUS), and is an IEEE Fellow. He was the founding general chair of the 1997 ACM/IEEE International Symposium on Physical Design, founding co-general chair of the ACM Workshop on System-Level Interconnect Prediction, and has served as general chair of the Design Automation Conference, the International Symposium on Quality Electronic Design, and the Electronic Design Processes Workshop. He served on the EDA Council's EDA 200X task force, which produced this report, and has provided analyses of worldwide research funding gaps for the SRC's CADTS and ICSS science areas since 2001. He defined the physical design roadmap as a member of the Design Tools and Test technology working group (TWG) for the 1997-1999 renewals of the International Technology Roadmap for Semiconductors (ITRS), and since 2000 has served as Chair or Co-Chair of the U.S. Design Technology Working Group, and of the Design International Technology Working Group, for the ITRS (with responsibility for the Design Chapter, the System Drivers Chapter, the associated tables, and the models of maximum on-chip frequency, layout density, and defect density in the Overall Roadmap Technology Characteristics).