UCSD VLSI CAD LABORATORY














Last Modified: October 11, 2006
Andrew B. Kahng
Professor of CSE and ECE
Computer Science and Engineering Dept
Electrical and Computer Engineering Dept
University of California, San Diego
San Diego, CA 92093-0114

Phone: (858) 822-4884
Fax: (858) 534-7029
Email: abk@cs.ucsd.edu
Office: EBU3B 2144, UCSD

Home page of Andrew Kahng

Areas of Interest

Professor Kahng's research interests include algorithms and methodologies for the computer-aided physical design of VLSI circuits, performance analysis of circuits and interconnects, discrete algorithms, and combinatorial and large-scale heuristic optimization. Major research foci include (1) the semiconductor design-manufacturing interface, especially the cost-effective mitigation and compensation of manufacturing process variability, (2) semiconductor technology and system roadmapping, and (3) fundamental algorithms and optimizations for (module, interconnect) layout synthesis in digital and mixed-signal designs at all levels of system hierarchy. Professor Kahng's group also has interests in other applied algorithmics contexts such as networking, bioinformatics, and computational commerce.

Biographical Sketch

Andrew B. Kahng (b. Oct. 1963, San Diego, CA) received the A.B. degree in applied mathematics (physics) from Harvard College, and from June 1983 to June 1986 was affiliated with Burroughs Corporation Micro Components Group in San Diego, where he worked in device physics, circuit simulation, and CAD for VLSI layout. He received the M.S. and Ph.D. degrees in computer science from the University of California at San Diego. He joined the UCLA computer science department as an assistant professor in July 1989, and became associate professor in July 1994 and full professor (at age 34) in July 1998. From April 1996 through September 1997, he was on sabbatical leave and leave of absence from UCLA, as Visiting Scientist at Cadence Design Systems, Inc. He resumed his duties at UCLA in Fall 1997, and from July 1998 to September 2000 served as the computer science department's vice-chair for graduate studies. Effective January 1, 2001 Professor Kahng joined UCSD as Professor in the CSE and ECE Departments. He served as Associate Chair of the UCSD CSE Department from 2003-2004. In October 2004, Professor Kahng co-founded Blaze DFM, Inc., an EDA software company that delivered new cost and yield optimizations at the IC design-manufacturing interface. He served as CTO of the company during a two-year leave of absence, returning to the university full-time in September 2006. The Blaze DFM core technology is responsible for substantial leakage power and total power reductions in such high-volume products as AMD/ATI Radeon graphics processor chips, and is embodied today in the TSMC Power Trim Service that enables low integrated-circuit power consumption and green products.

Professor Kahng is the author of 3 books and well over 350 journal and conference papers. He holds 17 issued U. S. patents. His 22 Ph.D. graduates (Robins, Hagen, Boese, Alpert, Tsao, Muddu, Huang, Masuko, Markov, Liu, Chen, Mantik, Xu, Wang, Reda, Gupta, Sharma, Muddu, Park, Topaloglu, Samadi, Jeong) have gone on to notable successes in both academia and industry. He has received NSF Research Initiation and Young Investigator awards, 13 Best Paper nominations, and 6 Best Paper awards (DAC, ISQED (2), ICCD, ASP-DAC/VLSI Design, and BACUS), and is an IEEE Fellow. He was the founding general chair of the 1997 ACM/IEEE International Symposium on Physical Design, founding co-general chair of the ACM Workshop on System-Level Interconnect Prediction, and has served as general chair of the Design Automation Conference, the International Symposium on Quality Electronic Design, and the Electronic Design Processes Workshop. He served on the EDA Council's EDA 200X task force, which produced this report, and has provided analyses of worldwide research funding gaps for the SRC's CADTS and ICSS science areas since 2001. He defined the physical design roadmap as a member of the Design Tools and Test technology working group (TWG) for the 1997-1999 renewals of the International Technology Roadmap for Semiconductors (ITRS), and since 2000 has served as Chair or Co-Chair of the U.S. Design Technology Working Group, and of the Design International Technology Working Group, for the ITRS (with responsibility for the Design Chapter, the System Drivers Chapter, the associated tables, and the models of maximum on-chip frequency, layout density, and defect density in the Overall Roadmap Technology Characteristics).

Selected Talks

  • "On Structure and Scaling in Optimization", May 17, 1991, Jacob Marschak Interdisciplinary Colloquium on Mathematics in the Social Sciences, abstract published in Mathematical Social Sciences 22 (1991), pp. 182-183.
  • "New Spectral Methods for Ratio Cut Partitioning and Clustering", May 29, 1991, UC Irvine ECE Department Colloquium.
  • "Issues in Performance-Driven Interconnection", July 31, 1991, Southern California VLSI CAD Colloquium, held at UC Irvine ICS Department.
  • "On Circuit Partitioning and the Intrinsic Rent Parameter", April 13, 1992, VLSI Colloquium, UC Berkeley EECS Department.
  • "On Cost Surfaces and Stochastic Hill-Climbing Variants", invited talk, April 29, 1992, ORSA Annual Meeting, Orlando.
  • "How to Partition a Circuit", May 14, 1992, UC Santa Cruz Computer Engineering Department Colloquium.
  • "On the Effective Design of High-Performance Routing Trees", April 12, 1993, VLSI Colloquium, UC Berkeley EECS Department.
  • "New Directions in Practical Large-Scale Optimization", May 3, 1993, VLSI Colloquium, UC Berkeley EECS Department; June 22, 1993, UC Santa Cruz Computer Engineering Department Colloquium. Also: Colloquium talks at UCSD Computer Science and Engineering Dept. (April 1994), UCLA Computer Science Dept. (May 1994), UCSB ECE Dept. (October 1994), Northwestern Univ. EECS Dept. (April 1995), etc.
  • "Parallel Dynamic Adaptive Search Algorithms", July 9, 1993, Mathematical Programming Society Symposium on Parallel Optimization, Madison WI.
  • "New Ideas in Finite-Time Global Optimization", invited talk, Dagstuhl-Seminar on Combinatorial Methods for Integrated Circuit Design, October 22-28, 1993, Schloss Dagstuhl, Germany.
  • "On Problem Structure and Amenability to Gradient Methods", invited talk, November 1, 1993, ORSA/TIMS National Meeting, Phoenix.
  • "Non-Monotone Strategies in Hill-Climbing Optimization", invited talk, November 2, 1993, ORSA/TIMS National Meeting, Phoenix.
  • "Parallel Dynamic Adaptive Search Algorithms", invited talk, TIMS/ORSA Joint National Meeting, Boston, April 24-27, 1994.
  • "Collective Action for Autonomous Robots", invited talk, May 9, 1995, U.S. Army Sensor Technology and Engineering Colloquium Series, Washington DC.
  • "Roadmaps Toward a Science of VLSI Design", invited plenary talk, May 13, 1996, VLSI CAD Track, IEEE Intl. Symposium on Circuits and Systems, Atlanta, May 1996. Also: Colloquium talk at University of Virginia Computer Science Dept. (December 1996).
  • "Futures and Core Algorithm Technologies for Physical Design", Distinguished Lecture Series, June 19, 1997, Cadence Design Systems, Inc, San Jose CA. Also: Colloquium talks at IBM Austin Research Laboratory (May 1997), University of Toronto EECG Dept. (June 1997), University of Waterloo Computer Science Dept. (June 1997), NASA Ames Research Center (July 1997), etc.
  • "Futures and Core Algorithm Technologies for Physical Design", Distinguished Lecture Talk, June 19, 1997.
  • "SIA Strategic Technology Council presentation" , January 24th, 2002.
  • "Michigan EECS Dept VLSI Seminar talk" , March 4th, 2002.
  • "ICCAD 2003 talk: Manufacturing Aware Physical Design" , November, 2003.
  • "CAD Research, Pay now or Pay later ..." ICCAD Monday Evening Panel, November 2006.
  • "Futures at the Design-Manufacturing Interface", KAIST EE Department, Daejeon, Korea, March 28, 2011.
  • "The Future of Signoff", opening keynote, TAU-2011, Santa Barbara, CA, March 31, 2011.
  • "Energy Efficiency and Resilience in Future ICs", Yale University, April 25, 2011.